Icestorm: LD1 (single, H) measurements

Code:

  ld1 { v0.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.001

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.001

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29872	2011	1	1008	1002	1002	1000	3000	7770	2000	1000	1000	1000	2000	1	1000	1000
62004	29453	2002	1	1001	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62005	29590	2002	1	1001	1000	1000	1000	3006	7768	2000	1000	1000	1000	2000	1	1000	1000
62004	29586	2002	1	1001	1000	1000	1000	3000	7762	2000	1000	1000	1000	2000	1	1000	1000
62004	29643	2002	1	1001	1000	1000	1000	3000	7762	2000	1000	1000	1000	2000	1	1000	1000
62004	29524	2002	1	1001	1000	1000	1000	3001	7810	2000	1000	1000	1000	2000	1	1000	1000
62004	29891	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	2000	1	1000	1000
62005	29488	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	2000	1	1000	1000
62004	29711	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	2000	1	1000	1000
62004	29506	2002	1	1001	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.h }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120225	70114	40101	20012	10001	30130	20031	10004	3209095	1257603	2575727	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60294	10016	30049	40006	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120050	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60302	10017	30049	40006	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120156	70024	40011	20012	10001	30040	20031	10004	3209019	1259221	2578586	60024	30032	10004	20008	60020	10000	30000	40001	10000	10000	40010
60024	120052	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010
60024	120045	70013	40011	20002	10000	30010	20000	10048	3215466	1262775	2584816	60287	30175	10048	20100	60020	10000	30000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10028	3209585	1259473	2579071	60156	30110	10028	20058	60120	10016	30049	40007	10000	10000	40010
60024	120047	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10015	3209208	1259339	2578801	60088	30069	10016	20033	60020	10000	30000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10000	3209141	1259294	2578699	60010	30020	10000	20000	60250	10036	30111	40025	10000	10000	40010
60025	120073	70022	40016	20005	10001	30043	20031	10003	3208934	1259062	2578287	60022	30030	10004	20008	120199	82337	12658	52118	41331	4253	59623
60024	120042	70013	40011	20002	10000	30013	20007	10004	3208884	1259166	2578471	60024	30032	10004	20008	60020	10000	30000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.h }[1], [x6]
  ld1 { v0.h }[1], [x6]
  ld1 { v0.h }[1], [x6]
  ld1 { v0.h }[1], [x6]
  ld1 { v0.h }[1], [x6]
  ld1 { v0.h }[1], [x6]
  ld1 { v0.h }[1], [x6]
  ld1 { v0.h }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	160159	160139	101	80006	80032	100	80026	80041	300	240419	4080190	160175	200	80045	80045	200	80004	160008	1	80000	80000	100
160204	160053	160105	101	80002	80002	100	80000	80002	300	240188	4079792	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160053	160105	101	80002	80002	100	80000	80041	300	240361	4080175	160175	200	80045	80045	200	80004	160008	1	80000	80000	100
160204	160053	160105	101	80002	80002	100	80000	80002	300	240188	4079792	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160205	160088	160143	101	80010	80032	100	80034	80002	300	240188	4079792	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160053	160105	101	80002	80002	100	80000	80002	300	240188	4079792	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160053	160105	101	80002	80002	100	80000	80002	300	240188	4079792	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160053	160105	101	80002	80002	100	80000	80002	300	240170	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160047	160104	101	80001	80002	100	80000	80040	300	240406	4080242	160174	200	80044	80044	4708	74869	142526	2042	72596	71220	2491
160205	160090	160143	101	80010	80032	100	80034	80002	300	240102	4079636	160102	200	80004	80004	200	80004	160008	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
162103	176955	161865	1103	80016	80746	1066	80060	80040	30	240408	4080190	160084	20	80044	80044	20	80044	160088	1	80000	80000	10
160024	160053	160016	11	80002	80003	10	80000	80000	30	240188	4079792	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160053	160013	11	80002	80000	10	80000	80000	30	240182	4079792	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160053	160013	11	80002	80000	10	80000	80000	30	240182	4079792	160010	20	80000	80000	20	80045	160090	1	80000	80000	10
160024	160053	160013	11	80002	80000	10	80000	80000	30	240182	4079792	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160053	160013	11	80002	80000	10	80000	80000	30	240182	4079792	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160053	160013	11	80002	80000	10	80000	80000	30	240182	4079792	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160053	160013	11	80002	80000	10	80000	80040	30	240358	4080190	160084	20	80044	80044	20	80000	160000	1	80000	80000	10
160024	160053	160013	11	80002	80000	10	80000	80000	30	240182	4079792	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160053	160013	11	80002	80000	10	80000	80000	30	240184	4079792	160010	20	80000	80000	20	80000	160000	1	80000	80000	10

LD1 (single, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations