Icestorm: LD1 (single, S) measurements

Code:

  ld1 { v0.s }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.001

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.001

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29715	2011	1	1008	1002	1002	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62004	29359	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62004	29355	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62004	29376	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62004	29376	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62004	29376	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62004	29542	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62004	29570	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000
62004	29590	2003	1	1002	1000	1000	1000	3000	7768	2000	1000	1000	1000	2000	1	1000	1000
62004	29744	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	2000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.s }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0048

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120154	70114	40101	20012	10001	30130	20031	10004	3208883	1257514	2575551	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3209098	1257740	2575963	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	30012	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120385	70024	40011	20012	10001	30040	20031	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60118	10017	30049	40006	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60118	10016	30049	40006	10000	10000	40010
60024	120050	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60114	10016	30049	40006	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60120	10016	30049	40006	10000	10000	40010
60024	120044	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208952	1259209	2578539	60010	30020	10000	20000	60020	10000	30000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.s }[1], [x6]
  ld1 { v0.s }[1], [x6]
  ld1 { v0.s }[1], [x6]
  ld1 { v0.s }[1], [x6]
  ld1 { v0.s }[1], [x6]
  ld1 { v0.s }[1], [x6]
  ld1 { v0.s }[1], [x6]
  ld1 { v0.s }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	160158	160139	101	80006	80032	100	80026	80002	300	240170	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160055	160105	101	80002	80002	100	80000	80002	300	240198	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160205	160090	160143	101	80010	80032	100	80034	80002	300	240170	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160055	160105	101	80002	80002	100	80000	80002	300	240176	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160055	160105	101	80002	80002	100	80000	80002	300	240188	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160055	160105	101	80002	80002	100	80000	80002	300	240170	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160055	160105	101	80002	80002	100	80000	80002	300	240170	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160055	160105	101	80002	80002	100	80000	80002	300	240170	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100
160204	160055	160105	101	80002	80002	100	80000	80040	300	240662	4080242	160174	200	80044	80044	200	80004	160008	1	80000	80000	100
160204	160055	160105	101	80002	80002	100	80000	80002	300	240170	4079844	160102	200	80004	80004	200	80004	160008	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	160159	160049	11	80006	80032	10	80026	80002	30	240200	4079792	160012	20	80004	80004	20	80000	160000	1	80000	80000	10
160024	160045	160012	11	80001	80000	10	80000	80000	30	240110	4079610	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160045	160012	11	80001	80000	10	80000	80000	30	240052	4079662	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160045	160012	11	80001	80000	10	80000	80002	30	240170	4079844	160012	20	80004	80004	20	80000	160000	1	80000	80000	10
160024	160047	160012	11	80001	80000	10	80000	80000	30	240074	4079636	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160047	160012	11	80001	80000	10	80000	80000	30	240074	4079636	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160047	160012	11	80001	80000	10	80000	80040	30	240304	4080226	160084	20	80044	80044	20	80000	160000	1	80000	80000	10
160024	160047	160012	11	80001	80000	10	80000	80000	30	240074	4079636	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	160047	160012	11	80001	80000	10	80000	80040	30	240304	4080226	160084	20	80044	80044	20	80000	160000	1	80000	80000	10
160024	160047	160012	11	80001	80000	10	80000	80000	30	240104	4079636	160010	20	80000	80000	20	80000	160000	1	80000	80000	10

LD1 (single, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations