Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (single, post-index, B)

Test 1: uops

Code:

  ld1 { v0.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.001

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.001

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6200529522301310031008100210021002100030003000776230001000100020002000100110001000
6200429286300210011001100010001000100030003000776230001000100020002000100110001000
6200429274300210011001100010001000100030003000776230001000100020002000100110001000
6200429278300210011001100010001000100030003000776230001000100020002000100110001000
6200429280300210011001100010001000100030003000776230001000100020002000100110001000
6200429278300210011001100010001000100030003000776230001000100020002000100110001000
6200429299300210011001100010001000100030003000776230001000100020002000100110001000
6200429299300210011001100010001000100030003000776230001000100020002000100110001000
6200529297300210011001100010001000100030003004776630001000100020002000100110001000
6200429278300210011001100010001000100030003028779030001000100020002000100110001000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.b }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6020512015580115501022001210001401322002410003319932294358119523007011330209100042000760218200083001150001100001000040100
6020412004980105501012000410000401042000610003319932294358119523007011330209100042000760218200083001150001100001000040100
6020412014280105501012000410000401042000610003319939194364519524187011330209100042000760218200083001150001100001000040100
6020412004980105501012000410000401042000610003319936494363619524007011330209100042000760218200083001150001100001000040100
6020412004980105501012000410000401042000610003319936494363619524007011330209100042000760272200283004050007100001000040100
6020412004980105501012000410000401042000610003319936494363619524007011330209100042000760218200083001150001100001000040100
6020412004980105501012000410000401042000610003319936494363619524007011330209100042000760218200083001150001100001000040100
6020412004980105501012000410000401042000610003319936494363619524007011330209100042000760218200083001150001100001000040100
6020412004980105501012000410000401042000610003319936494363619524007011330209100042000760218200083001150001100001000040100
6020412004980105501012000410000401042000610003319936494363619524007011330209100042000760280200243003750008100001000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6002512015780025500122001210001400422002410003319935894457419542377002330029100042000760098200283004150007100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010012320008294482019547507008230059100142002760020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004880013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.b }[1], [x6], x8
  ld1 { v0.b }[1], [x6], x8
  ld1 { v0.b }[1], [x6], x8
  ld1 { v0.b }[1], [x6], x8
  ld1 { v0.b }[1], [x6], x8
  ld1 { v0.b }[1], [x6], x8
  ld1 { v0.b }[1], [x6], x8
  ld1 { v0.b }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020516015324017580133800108003280134800298000528051728025840396922401142008000580005200160010160010800048000080000100
16020516008824017780133800128003280134800338000528050128024240397322401142008000580005200160008160008800038000080000100
16020416005324010980103800048000280104800038000428047328021440397772401112008000480004200160008160008800038000080000100
16020416005324010980103800048000280104800038000428047328021440397772401112008000480004200160008160008800038000080000100
16020416005324010980103800048000280104800038000428047328021440397772401112008000480004200160068160068800338000080000100
16020416005324010980103800048000280104800038000428047328021440397772401112008000480004200160008160008800038000080000100
16020416005324010980103800048000280104800038000428047328021440397772401112008000480004200160008160008800038000080000100
16020416005324010980103800048000280104800038000428047328021440397772401112008000480004200160008160008800038000080000100
16020416005324010980103800048000280104800038000428047328021440397772401112008000480004200160008160008800038000080000100
16020416005324010980103800048000280104800038000428047328021440397772401112008000480004200160008160008800038000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002516015124008580043800108003280044800298000428024828025940398222400212080004800042016000016000080001800008000010
16002416005324001580011800048000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416005324001580011800048000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416005324001580011800048000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416005324001580011800048000080010800008000028023528024840398022400102080000800002016000016000080001800008000010
16002416005324001580011800048000080010800008003428067528068440402042401112080034800342016000016000080001800008000010
16002416005324001580011800048000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416005324001580011800048000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416005324001580011800048000080010800008000028023528082240398022400102080000800002016000016000080001800008000010
16002516008824008780043800128003280044800338000028023528024640398022400102080000800002016000016000080001800008000010