Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (single, post-index, S)

Test 1: uops

Code:

  ld1 { v0.s }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6200529505301310031008100210021002100030003000777030001000100020002000100110001000
6200429338300410011003100010001000100030003000777030001000100020002000100110001000
6200429347300310011002100010001000100030003000777030001000100020002000100110001000
6200429363300310011002100010001000100030003000777030001000100020002000100110001000
6200429357300310011002100010001000100030003000777030001000100020002000100110001000
6200429360300310011002100010001000100030003000777030001000100020002000100110001000
6200429419300310011002100010001000100030003000777030001000100020002000100110001000
6200429482300310011002100010001000100030003000776730001000100020002000100110001000
6200429400300310011002100010001000100030003000776730001000100020002000100110001000
6200429418300310011002100010001000100030003000776730001000100020002000100110001000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.s }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6020512015580115501022001210001401322002410003319927294353119522117011330209100042000760218200083001150001100001000040100
6020412004280103501012000210000401042000610012319958794369219525097017230239100142002760218200083001150001100001000040100
6020412004280103501012000210000401042000610003319917594358019522747011330209100042000760218200083001150001100001000040100
6020412004280103501012000210000401042000610003319917594358019522747011330209100042000760218200083001150001100001000040100
6020412004280103501012000210000401042000610003319917594358019522747011330209100042000760218200083001150001100001000040100
6020412004280103501012000210000401042000610003319917594358019522747011330209100042000760218200083001150001100001000040100
6020412004280103501012000210000401042000610012320085694411219533327017230239100142002760218200083001150001100001000040100
6020412004280103501012000210000401042000610003319936494363619524007011330209100042000760218200083001150001100001000040100
6020412004980105501012000410000401042000610003319917594358019522747011330209100042000760218200083001150001100001000040100
6020412004280103501012000210000401042000610003319917594358019522747011330209100042000760218200083001150001100001000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6002512015680025500122001210001400422002410000319932994453319541557001030020100002000060098200263003950007100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004780015500112000410000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412006080013500112000210000400102000010000319929794457119542037001030020100002000060080200203003050007100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004780015500112000410000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010
6002412004080013500112000210000400102000010000319918994453519541347001030020100002000060020200003000050001100001000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020516015924017580133800108003280134800298000528050128024240397322401142008000580005202160068160068800348000080000100
16020416004524010780103800028000280104800038000528051328022140395242401142008000580005200160008160008800038000080000100
16020416004524010780103800028000280104800038000428048528019340395692401112008000480004200160008160008800038000080000100
16020416004524010780103800028000280104800038000428048528019340395692401112008000480004200160008160008800038000080000100
16020416004524010780103800028000280104800038003428091228061840399512402012008003480034200160008160008800038000080000100
16020416004524010780103800028000280104800038000428048528019340395692401112008000480004200160008160008800038000080000100
16020416004524010780103800028000280104800038000428048528019340395692401112008000480004200160008160008800038000080000100
16020416004524010780103800028000280104800038000428048528019340395692401112008000480004200160008160008800038000080000100
16020516008024017580133800108003280134800338000428048528030340395692401112008000480004200160008160008800038000080000100
16020416004524010780103800028000280104800038000428048528019340395692401112008000480004200160008160008800038000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002516029324008580043800108003280044800298000028023528024640398022400102080000800002016000016000080001800008000010
16002416004524001380011800028000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416005324001580011800048000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416005324001580011800048000080010800008003428067528100940402042401112080034800342016000016000080001800008000010
16002416004524001380011800028000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416004524001380011800028000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416004524001380011800028000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002516008024008580043800108003280044800338000028023528024640398022400102080000800002016000016000080001800008000010
16002416004524001380011800028000080010800008000028023528024640398022400102080000800002016000016000080001800008000010
16002416004524001380011800028000080010800008000028023528024640398022400102080000800002016000016000080001800008000010