Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (16B)

Test 1: uops

Code:

  ld2r { v0.16b, v1.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630052962030311202810022004100030001529030001000200010002000110002000
630042939630051200410002000100030001529030001000200010002000110002000
630042970530051200410002000100030011529230001000200010002000110002000
630042937330051200410002000100030001529030001000200010002000110002000
630042934430051200410002000100030001529030001000200010002000110002000
630042934430051200410002000100030001529030001000200010002000110002000
630042936530051200410002000100030001529030001000200010002000110002000
630042937030051200410002000100030001529030001000200010002000110002000
630042934630051200410002000100030001529030001000200010002000110002000
630042937830051200410002000100030001529030001000200010002000110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.16b, v1.16b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120153801204010130018100013013030027100033208839120879730844657010830208100033000960216100033000940001100002000040100
70204120040801044010130003100003010330002100143210362120949430859517017930242100153004360216100033000940001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120045801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120040801044010130003100003010330002100033208817120890730844727010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120041801044010130003100003010330002100033208817120891030844727010830208100033000960216100033000940001100002000040100
70205120132801144010630007100013013330032100033208817120890730844727010830208100033000960216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120156800304001130018100013004030027100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060104100153004340006100002000040010
70024120074800204001130009100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120052800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120052800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003211590121041330870157001030020100003000060020100003000040001100002000040010
70024120051800174001130006100003001030000100003209133120944630846717001030020100003000060020100003000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.16b, v1.16b }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120518801204010130018100013013030027100033208756120882930844017010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208741120881830843877010830208100033000960216100033000940001100002000040100
70204120043801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960280100153004540005100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100143209576120918530851947017930244100153004560284100153004340006100002000040100
70204120051801044010130003100003010330002100143211533120982330870137018130244100153004560284100153004340006100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120166800304001130018100013004030027100033208789120930130843497001830028100033000960020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060108100153004540006100002000040010
70024120047800174001130006100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208890120935630844467001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208836120933330843937001030020100003000060020100003000040001100002000040010
70024120043800144001130003100003001030000100143209372120955930849117008930062100153004360020100003000040001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.16b, v1.16b }, [x6]
  ld2r { v0.16b, v1.16b }, [x6]
  ld2r { v0.16b, v1.16b }, [x6]
  ld2r { v0.16b, v1.16b }, [x6]
  ld2r { v0.16b, v1.16b }, [x6]
  ld2r { v0.16b, v1.16b }, [x6]
  ld2r { v0.16b, v1.16b }, [x6]
  ld2r { v0.16b, v1.16b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
2402058015624019110116007080020100160034800063002400359733302401142008000716001320080007160013180000160000100
24020480061240127101160022800041001600088000630024002516002822401142008000716001320080007160013180000160000100
24020480048240121101160016800041001600088000630024002516002822401142008000716001320080007160013180000160000100
24020480048240121101160016800041001600088000630024002516002822401142008000716001320080007160013180000160000100
24020480048240121101160016800041001600088000630024002516002822401142008000716001320080007160013180000160000100
24020480048240121101160016800041001600088000630024157716010662401142008000716001320080037160071180000160000100
24020480048240121101160016800041001600088000630024002316003862401142008000716001320080007160013180000160000100
24020480048240121101160016800041001600088000630024002516002822401142008000716001320080007160013180000160000100
24020480048240121101160016800041001600088000630024002516002822401142008000716001320080007160013180000160000100
24020480048240121101160016800041001600088000630024002516002822401142008000716001320080007160013180000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002680217240157111601048004210160080800083024004010244702400282080008160014208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208003716007118000016000010
24002580167240092111600548002710160056800063024003612166142400242080007160013208000016000018000016000010
24002480057240031111600208000010160000800003024001816004962400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010