Icestorm: LD2R (1D) measurements

Code:

  ld2r { v0.1d, v1.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
63005	31667	3033	1	2030	1002	0	2004	1000	3003	15296	3000	1000	2000	1000	2000	1	1000	2000
63004	29315	3005	1	2004	1000	0	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29303	3005	1	2004	1000	0	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29303	3005	1	2004	1000	0	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29308	3005	1	2004	1000	0	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29313	3005	1	2004	1000	0	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29308	3005	1	2004	1000	0	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29305	3005	1	2004	1000	0	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29309	3005	1	2004	1000	0	2000	1000	3005	15300	3000	1000	2000	1000	2000	1	1000	2000
63004	30186	3005	1	2004	1000	0	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.1d, v1.1d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70206	120185	80130	40106	30022	10002	30160	30057	10003	3209242	1209022	3084864	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208876	1208868	3084512	70108	30208	10003	30009	60284	10015	30046	40006	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3209114	1209021	3084751	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208952	1208958	3084595	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60288	10015	30045	40006	10000	20000	40100
70204	120050	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208979	1208969	3084621	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120146	80030	40011	30018	10001	30040	30027	10003	3208978	1209371	3084524	70018	30028	10003	30009	60108	10015	30045	40006	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60108	10015	30045	40006	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.1d, v1.1d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120157	80120	40101	30018	10001	30130	30027	10003	3208908	1208828	3084529	70108	30208	10003	30009	60284	10015	30045	40006	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208979	1208967	3084619	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3209006	1208978	3084645	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208979	1208967	3084619	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120134	80107	40101	30006	10000	30103	30002	10003	3209195	1209050	3084822	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208979	1208967	3084619	70108	30208	10003	30009	60288	10015	30043	40006	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208979	1208967	3084619	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208979	1208967	3084619	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208979	1208967	3084619	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120052	80107	40101	30006	10000	30103	30002	10003	3209478	1209058	3085074	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120154	80030	40011	30018	10001	30040	30027	10003	3209032	1209391	3084572	70018	30028	10003	30009	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120082	80027	40016	30010	10001	30043	30032	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120163	80027	40016	30010	10001	30043	30032	10000	3209160	1209457	3084697	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30013	30002	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3209187	1209470	3084725	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120147	80029	40015	30012	10002	30043	30031	10026	3211883	1210521	3087289	70161	30100	10027	30081	60020	10000	30000	40001	10000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240205	80174	240193	101	160072	80020	100	160034	80006	300	240035	986110	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80430	240443	101	160222	80120	100	160237	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80060	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80073	240125	101	160020	80004	100	160008	80006	300	240041	1344522	240114	200	80007	160013	30565	90182	129999	11811	76814	129966	15954
240204	80056	240125	101	160020	80004	100	160008	80006	300	240046	1600542	240114	200	80007	160013	200	80034	160066	1	80000	160000	100
240205	80107	240184	101	160056	80027	100	160056	80006	300	240098	1222344	240114	200	80007	160013	200	80033	160063	1	80000	160000	100
240204	80428	240445	101	160224	80120	100	160237	80006	300	240170	1600450	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240052	1600438	240114	200	80007	160013	200	80123	160241	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240025	80150	240101	11	160070	80020	10	160034	80000	30	240067	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80048	240027	11	160016	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80035	160069	1	80000	160000	10
240024	80048	240027	11	160016	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80048	240027	11	160016	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80048	240027	11	160016	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80048	240027	11	160016	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80048	240027	11	160016	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80048	240027	11	160016	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80048	240027	11	160016	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80037	160071	1	80000	160000	10

LD2R (1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations