Icestorm: LD2R (2D) measurements

Code:

  ld2r { v0.2d, v1.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
63005	29632	3031	1	2028	1002	2004	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29318	3005	1	2004	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29311	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29317	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29290	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29348	3005	1	2004	1000	2000	1000	3002	15278	3000	1000	2000	1000	2000	1	1000	2000
63004	29484	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29322	3003	1	2002	1000	2000	1000	3000	15276	3000	1000	2000	1000	2000	1	1000	2000
63004	29374	3003	1	2002	1000	2000	1000	3005	15284	3000	1000	2000	1000	2000	1	1000	2000
63005	29668	3006	1	2004	1001	2002	1000	3000	15278	3000	1000	2000	1000	2000	1	1000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2d, v1.2d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70204	120074	80110	40101	30009	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70205	120077	80116	40105	30009	10002	30133	30031	10003	3209104	1208961	3084730	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70205	120080	80117	40106	30010	10001	30133	30032	10003	3208952	1208958	3084595	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208979	1208967	3084619	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120156	80030	40011	30018	10001	30040	30027	10003	3209032	1209391	3084574	70018	30028	10003	30009	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120082	80027	40016	30010	10001	30043	30032	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60106	10015	30046	40006	10000	20000	40010
70024	120050	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120130	80017	40011	30006	10000	30010	30000	10000	3209160	1209457	3084697	70010	30020	10000	30000	60036	10003	30009	40001	10000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2d, v1.2d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120161	80120	40101	30018	10001	30130	30027	10003	3208866	1208807	3084492	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70205	120073	80114	40106	30007	10001	30133	30032	10003	3209222	1209067	3084862	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208844	1208917	3084494	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60288	10015	30044	40006	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208763	1208887	3084419	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70205	120242	80123	40106	30016	10001	30133	30032	10090	3214468	1210916	3088005	70505	30500	10093	30153	60354	10027	30080	40010	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120155	80030	40011	30018	10001	30040	30027	10000	3209009	1209337	3084543	70010	30020	10000	30000	60036	10003	30009	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60110	10015	30044	40006	10000	20000	40010
70024	120052	80017	40011	30006	10000	30010	30000	10048	3215586	1211867	3091075	70310	30164	10048	30141	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120080	80027	40016	30010	10001	30043	30032	10000	3209187	1209470	3084725	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60104	10015	30043	40006	10000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.2d, v1.2d }, [x6]
  ld2r { v0.2d, v1.2d }, [x6]
  ld2r { v0.2d, v1.2d }, [x6]
  ld2r { v0.2d, v1.2d }, [x6]
  ld2r { v0.2d, v1.2d }, [x6]
  ld2r { v0.2d, v1.2d }, [x6]
  ld2r { v0.2d, v1.2d }, [x6]
  ld2r { v0.2d, v1.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240205	80168	240193	101	160072	80020	100	160034	80006	300	240034	1344458	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240205	80091	240190	101	160058	80031	100	160064	80006	300	240394	1390532	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240065	1600594	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240046	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80058	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80037	160071	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240025	80172	240106	11	160074	80021	10	160036	80006	30	240034	1216458	240024	20	80007	160013	20	80000	160000	1	80000	160000	10
240024	80054	240031	11	160020	80000	10	160000	80000	30	240013	1600188	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80046	240023	11	160012	80000	10	160000	80000	30	240024	1600188	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80046	240023	11	160012	80000	10	160000	80000	30	240013	1600288	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80046	240023	11	160012	80000	10	160000	80000	30	240013	1600188	240010	20	80000	160000	20	80037	160071	1	80000	160000	10
240024	80046	240023	11	160012	80000	10	160000	80000	30	240054	1600196	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80046	240023	11	160012	80000	10	160000	80000	30	240535	1600404	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80046	240023	11	160012	80000	10	160000	80000	30	240013	1600188	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80046	240023	11	160012	80000	10	160000	80000	30	240007	1600236	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80046	240023	11	160012	80000	10	160000	80000	30	240013	1600188	240010	20	80000	160000	20	80000	160000	1	80000	160000	10

LD2R (2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations