Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (2S)

Test 1: uops

Code:

  ld2r { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630052969930331203010022004100030001528430001000200010002000110002000
630042949930051200410002000100030001527030001000200010002000110002000
630042938830031200210002000100030001527030001000200010002000110002000
630042943030031200210002000100030001528430001000200010002000110002000
630042947530031200210002000100030001527030001000200010002000110002000
630042943030051200410002000100030001527030001000200010002000110002000
630042944830031200210002000100030001527030001000200010002000110002000
630042938330051200410002000100030001527030001000200010002000110002000
630042942830031200210002000100030001528430001000200010002000110002000
630042947530031200210002000100030001528430001000200010002000110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2s, v1.2s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120150801204010130018100013013030027100033208888120887630845227010830208100033000960216100033000940001100002000040100
70205120154801234010630016100013013330032100033209593120914330851807010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100153209247120905530848727018030244100153004460216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70205120094801174010630010100013013330032100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033209006120898030846477010830208100033000960216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120148800304001130018100013004030027100023209032120939130845747001730026100033000960036100033000940001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100143210587121003330860657008930063100153004660020100003000040001100002000040010
70024120111800174001130006100003001030000100003209349120953430848797001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70025120082800274001630010100013004330032100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2s, v1.2s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120147801204010130018100013013030027100033208839120879730844677010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100143209163120902430848017017830240100153004560216100033000940001100002000040100
70204120052801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120050801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70205120080801174010630010100013013330032100143211307120985130868377017930242100153004360216100033000940001100002000040100
70204120114801074010130006100003010330002100033209330120910930849597010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120156800304001130018100013004030027100003209052120941330845937001030020100003000060108100153004440006100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
700241200498001740011300061000030010300001001532093961209579308492570090300651001530044565569424282733764294091881837645
70024120055800174001130006100003001030000100003209133120944430846717001030020100003000060020100003000040001100002000040010
70024120053800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
2402058018224019110116007080020100160034800063002400349860782401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024006216004422401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003616005422401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080037160071180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024006316004462401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024007516004462401142008000716001320080007160013180000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580177240103111600728002010160034800063024003412164582400242080007160013208000016000018000016000010
24002480054240031111600208000010160000800003024001316001882400102080000160000208000016000018000016000010
24002580084240088111600468003110160064800003024001716004442400102080000160000208000016000018000016000010
24002480046240023111600128000010160000800003024001316001882400102080000160000208000016000018000016000010
24002480046240023111600128000010160000800003024001316001882400102080000160000208000016000018000016000010
24002480046240023111600128000010160000800003024001316001882400102080000160000208000016000018000016000010
24002480046240023111600128000010160000800003024001316001882400102080000160000208000016000018000016000010
24002580103240106111600648003110160064800003024002016014322400102080000160000208000016000018000016000010
24002480046240023111600128000010160000800003024001316001882400102080000160000208003516006918000016000010
24002480054240031111600208000010160000800003024001316001882400102080000160000208000016000018000016000010