Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld2r { v0.4h, v1.4h }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 3.000
Issues: 3.004
Integer unit issues: 0.001
Load/store unit issues: 1.000
SIMD/FP unit issues: 2.004
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) |
63005 | 29726 | 3033 | 1 | 2030 | 1002 | 2004 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 29577 | 3005 | 1 | 2004 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 29486 | 3005 | 1 | 2004 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 29844 | 3005 | 1 | 2004 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 30312 | 3005 | 1 | 2004 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 29739 | 3005 | 1 | 2004 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 29672 | 3005 | 1 | 2004 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 29865 | 3005 | 1 | 2004 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 29684 | 3005 | 1 | 2004 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
63004 | 31091 | 3009 | 1 | 2008 | 1000 | 2000 | 1000 | 3000 | 15290 | 3000 | 1000 | 2000 | 1000 | 2000 | 1 | 1000 | 2000 |
Chain cycles: 3
Code:
ld2r { v0.4h, v1.4h }, [x6] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0047
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
70205 | 120154 | 80120 | 40101 | 30018 | 10001 | 30130 | 30027 | 10003 | 3208888 | 1208876 | 3084524 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70205 | 120116 | 80117 | 40106 | 30010 | 10001 | 30133 | 30032 | 10003 | 3208925 | 1208947 | 3084569 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120047 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208952 | 1208958 | 3084595 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120047 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208925 | 1208947 | 3084569 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120047 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208925 | 1208947 | 3084569 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120047 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208925 | 1208947 | 3084569 | 70108 | 30208 | 10003 | 30009 | 60290 | 10015 | 30044 | 40006 | 10000 | 20000 | 40100 |
70204 | 120047 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208925 | 1208947 | 3084569 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120047 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208925 | 1208947 | 3084569 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120047 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208925 | 1208947 | 3084569 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120047 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208925 | 1208947 | 3084569 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
Result (median cycles for code, minus 3 chain cycles): 9.0049
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
70025 | 120158 | 80030 | 40011 | 30018 | 10001 | 30040 | 30027 | 10000 | 3209015 | 1209342 | 3084546 | 70010 | 30020 | 10000 | 30000 | 60036 | 10003 | 30009 | 40001 | 10000 | 20000 | 40010 |
70024 | 120047 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10014 | 3209342 | 1209549 | 3084876 | 70089 | 30063 | 10015 | 30046 | 60108 | 10015 | 30045 | 40006 | 10000 | 20000 | 40010 |
70024 | 120059 | 80017 | 40011 | 30006 | 10000 | 30013 | 30002 | 10000 | 3209079 | 1209424 | 3084619 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10014 | 3209399 | 1209573 | 3084928 | 70089 | 30064 | 10015 | 30045 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120050 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10014 | 3209504 | 1209603 | 3085031 | 70089 | 30062 | 10015 | 30043 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
Chain cycles: 3
Code:
ld2r { v0.4h, v1.4h }, [x6] fmov x1, d1 eor x8, x8, x1 eor x8, x8, x1 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0049
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
70205 | 120148 | 80120 | 40101 | 30018 | 10001 | 30130 | 30027 | 10003 | 3208908 | 1208828 | 3084529 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70205 | 120082 | 80117 | 40106 | 30010 | 10001 | 30133 | 30032 | 10003 | 3208979 | 1208967 | 3084619 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120049 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208979 | 1208967 | 3084619 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120049 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208979 | 1208967 | 3084619 | 70108 | 30208 | 10003 | 30009 | 43408 | 7212 | 21636 | 28791 | 7197 | 14394 | 28855 |
70204 | 120052 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208979 | 1208967 | 3084619 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120049 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208979 | 1208967 | 3084619 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120049 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208979 | 1208967 | 3084619 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120049 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208979 | 1208967 | 3084619 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
70204 | 120049 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3208979 | 1208967 | 3084619 | 70108 | 30208 | 10003 | 30009 | 60286 | 10015 | 30046 | 40006 | 10000 | 20000 | 40100 |
70204 | 120049 | 80107 | 40101 | 30006 | 10000 | 30103 | 30002 | 10003 | 3209087 | 1209011 | 3084723 | 70108 | 30208 | 10003 | 30009 | 60216 | 10003 | 30009 | 40001 | 10000 | 20000 | 40100 |
Result (median cycles for code, minus 3 chain cycles): 9.0049
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
70025 | 120150 | 80030 | 40011 | 30018 | 10001 | 30040 | 30027 | 10051 | 3214673 | 1211599 | 3090186 | 70318 | 30171 | 10051 | 30152 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209187 | 1209468 | 3084723 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120052 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60110 | 10015 | 30044 | 40006 | 10000 | 20000 | 40010 |
70024 | 120052 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10046 | 3215347 | 1211821 | 3090841 | 70308 | 30164 | 10048 | 30145 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120052 | 80017 | 40011 | 30006 | 10000 | 30013 | 30002 | 10000 | 3209484 | 1209588 | 3085009 | 70010 | 30020 | 10000 | 30000 | 60308 | 10048 | 30147 | 40033 | 10000 | 20000 | 40010 |
70024 | 120051 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120049 | 80017 | 40011 | 30006 | 10000 | 30010 | 30000 | 10000 | 3209133 | 1209446 | 3084671 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70024 | 120428 | 80081 | 40043 | 30030 | 10008 | 30142 | 30120 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
70025 | 120085 | 80027 | 40016 | 30010 | 10001 | 30043 | 30032 | 10000 | 3209052 | 1209413 | 3084593 | 70010 | 30020 | 10000 | 30000 | 60020 | 10000 | 30000 | 40001 | 10000 | 20000 | 40010 |
Count: 8
Code:
ld2r { v0.4h, v1.4h }, [x6] ld2r { v0.4h, v1.4h }, [x6] ld2r { v0.4h, v1.4h }, [x6] ld2r { v0.4h, v1.4h }, [x6] ld2r { v0.4h, v1.4h }, [x6] ld2r { v0.4h, v1.4h }, [x6] ld2r { v0.4h, v1.4h }, [x6] ld2r { v0.4h, v1.4h }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
240205 | 80387 | 240196 | 101 | 160074 | 80021 | 100 | 160036 | 80006 | 300 | 240035 | 1024510 | 240114 | 200 | 80007 | 160013 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
240204 | 80061 | 240127 | 101 | 160022 | 80004 | 100 | 160008 | 80006 | 300 | 240035 | 1600490 | 240114 | 200 | 80007 | 160013 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
240204 | 80056 | 240125 | 101 | 160020 | 80004 | 100 | 160008 | 80006 | 300 | 240035 | 1600490 | 240114 | 200 | 80007 | 160013 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
240204 | 80056 | 240125 | 101 | 160020 | 80004 | 100 | 160008 | 80034 | 300 | 240118 | 1429040 | 240196 | 200 | 80035 | 160069 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
240205 | 80092 | 240187 | 101 | 160056 | 80030 | 100 | 160062 | 80006 | 300 | 240313 | 1600490 | 240114 | 200 | 80007 | 160013 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
240204 | 80056 | 240125 | 101 | 160020 | 80004 | 100 | 160008 | 80006 | 300 | 240035 | 1600490 | 240114 | 200 | 80007 | 160013 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
240204 | 80056 | 240125 | 101 | 160020 | 80004 | 100 | 160008 | 80037 | 300 | 240126 | 1221052 | 240201 | 200 | 80037 | 160071 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
240204 | 80056 | 240125 | 101 | 160020 | 80004 | 100 | 160008 | 80031 | 300 | 241118 | 1559312 | 240185 | 200 | 80032 | 160062 | 200 | 80064 | 160126 | 1 | 80000 | 160000 | 100 |
240204 | 80060 | 240125 | 101 | 160020 | 80004 | 100 | 160008 | 80006 | 300 | 240034 | 1024478 | 240114 | 200 | 80007 | 160013 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
240204 | 80054 | 240125 | 101 | 160020 | 80004 | 100 | 160008 | 80006 | 300 | 240046 | 1600438 | 240114 | 200 | 80007 | 160013 | 200 | 80007 | 160013 | 1 | 80000 | 160000 | 100 |
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
240025 | 80171 | 240103 | 11 | 160072 | 80020 | 10 | 160034 | 80006 | 30 | 240035 | 1216510 | 240024 | 20 | 80007 | 160013 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |
240024 | 80048 | 240027 | 11 | 160016 | 80000 | 10 | 160000 | 80000 | 30 | 240007 | 1600236 | 240010 | 20 | 80000 | 160000 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |
240024 | 80048 | 240027 | 11 | 160016 | 80000 | 10 | 160000 | 80000 | 30 | 240007 | 1600236 | 240010 | 20 | 80000 | 160000 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |
240024 | 80048 | 240027 | 11 | 160016 | 80000 | 10 | 160000 | 80036 | 30 | 240113 | 1303380 | 240110 | 20 | 80037 | 160071 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |
240024 | 80048 | 240027 | 11 | 160016 | 80000 | 10 | 160000 | 80000 | 30 | 240007 | 1600236 | 240010 | 20 | 80000 | 160000 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |
240024 | 80048 | 240027 | 11 | 160016 | 80000 | 10 | 160000 | 80000 | 30 | 240007 | 1600236 | 240010 | 20 | 80000 | 160000 | 20 | 80029 | 160056 | 1 | 80000 | 160000 | 10 |
240024 | 80056 | 240031 | 11 | 160020 | 80000 | 10 | 160000 | 80000 | 30 | 240134 | 1600240 | 240010 | 20 | 80000 | 160000 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |
240024 | 80048 | 240027 | 11 | 160016 | 80000 | 10 | 160000 | 80000 | 30 | 240007 | 1600236 | 240010 | 20 | 80000 | 160000 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |
240025 | 80120 | 240091 | 11 | 160050 | 80030 | 10 | 160062 | 80006 | 30 | 240309 | 1358948 | 240024 | 20 | 80007 | 160013 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |
240024 | 80046 | 240023 | 11 | 160012 | 80000 | 10 | 160000 | 80000 | 30 | 240013 | 1600188 | 240010 | 20 | 80000 | 160000 | 20 | 80000 | 160000 | 1 | 80000 | 160000 | 10 |