Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (4H)

Test 1: uops

Code:

  ld2r { v0.4h, v1.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630052972630331203010022004100030001529030001000200010002000110002000
630042957730051200410002000100030001529030001000200010002000110002000
630042948630051200410002000100030001529030001000200010002000110002000
630042984430051200410002000100030001529030001000200010002000110002000
630043031230051200410002000100030001529030001000200010002000110002000
630042973930051200410002000100030001529030001000200010002000110002000
630042967230051200410002000100030001529030001000200010002000110002000
630042986530051200410002000100030001529030001000200010002000110002000
630042968430051200410002000100030001529030001000200010002000110002000
630043109130091200810002000100030001529030001000200010002000110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4h, v1.4h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120154801204010130018100013013030027100033208888120887630845247010830208100033000960216100033000940001100002000040100
70205120116801174010630010100013013330032100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208952120895830845957010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960290100153004440006100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120158800304001130018100013004030027100003209015120934230845467001030020100003000060036100033000940001100002000040010
70024120047800174001130006100003001030000100143209342120954930848767008930063100153004660108100153004540006100002000040010
70024120059800174001130006100003001330002100003209079120942430846197001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100143209399120957330849287008930064100153004560020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120050800174001130006100003001030000100143209504120960330850317008930062100153004360020100003000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4h, v1.4h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120148801204010130018100013013030027100033208908120882830845297010830208100033000960216100033000940001100002000040100
70205120082801174010630010100013013330032100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
702041200498010740101300061000030103300021000332089791208967308461970108302081000330009434087212216362879171971439428855
70204120052801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960286100153004640006100002000040100
70204120049801074010130006100003010330002100033209087120901130847237010830208100033000960216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120150800304001130018100013004030027100513214673121159930901867031830171100513015260020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209187120946830847237001030020100003000060020100003000040001100002000040010
70024120052800174001130006100003001030000100003209052120941330845937001030020100003000060110100153004440006100002000040010
70024120052800174001130006100003001030000100463215347121182130908417030830164100483014560020100003000040001100002000040010
70024120052800174001130006100003001330002100003209484120958830850097001030020100003000060308100483014740033100002000040010
70024120051800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209133120944630846717001030020100003000060020100003000040001100002000040010
70024120428800814004330030100083014230120100003209052120941330845937001030020100003000060020100003000040001100002000040010
70025120085800274001630010100013004330032100003209052120941330845937001030020100003000060020100003000040001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.4h, v1.4h }, [x6]
  ld2r { v0.4h, v1.4h }, [x6]
  ld2r { v0.4h, v1.4h }, [x6]
  ld2r { v0.4h, v1.4h }, [x6]
  ld2r { v0.4h, v1.4h }, [x6]
  ld2r { v0.4h, v1.4h }, [x6]
  ld2r { v0.4h, v1.4h }, [x6]
  ld2r { v0.4h, v1.4h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580387240196101160074800211001600368000630024003510245102401142008000716001320080007160013180000160000100
24020480061240127101160022800041001600088000630024003516004902401142008000716001320080007160013180000160000100
24020480056240125101160020800041001600088000630024003516004902401142008000716001320080007160013180000160000100
24020480056240125101160020800041001600088003430024011814290402401962008003516006920080007160013180000160000100
24020580092240187101160056800301001600628000630024031316004902401142008000716001320080007160013180000160000100
24020480056240125101160020800041001600088000630024003516004902401142008000716001320080007160013180000160000100
24020480056240125101160020800041001600088003730024012612210522402012008003716007120080007160013180000160000100
24020480056240125101160020800041001600088003130024111815593122401852008003216006220080064160126180000160000100
24020480060240125101160020800041001600088000630024003410244782401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024004616004382401142008000716001320080007160013180000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580171240103111600728002010160034800063024003512165102400242080007160013208000016000018000016000010
24002480048240027111600168000010160000800003024000716002362400102080000160000208000016000018000016000010
24002480048240027111600168000010160000800003024000716002362400102080000160000208000016000018000016000010
24002480048240027111600168000010160000800363024011313033802401102080037160071208000016000018000016000010
24002480048240027111600168000010160000800003024000716002362400102080000160000208000016000018000016000010
24002480048240027111600168000010160000800003024000716002362400102080000160000208002916005618000016000010
24002480056240031111600208000010160000800003024013416002402400102080000160000208000016000018000016000010
24002480048240027111600168000010160000800003024000716002362400102080000160000208000016000018000016000010
24002580120240091111600508003010160062800063024030913589482400242080007160013208000016000018000016000010
24002480046240023111600128000010160000800003024001316001882400102080000160000208000016000018000016000010