Icestorm: LD2R (4S) measurements

Code:

  ld2r { v0.4s, v1.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
63005	29613	3031	1	2028	1002	0	2004	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29593	3005	1	2004	1000	0	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29532	3005	1	2004	1000	0	2000	1000	3000	15278	3000	1000	2000	1000	2000	1	1000	2000
63004	30170	3005	1	2004	1000	0	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	30121	3005	1	2004	1000	0	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29891	3005	1	2004	1000	0	2000	1000	3000	15282	3000	1000	2000	1000	2000	1	1000	2000
63004	29865	3005	1	2004	1000	0	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29604	3005	1	2004	1000	0	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29796	3005	1	2004	1000	0	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29667	3005	1	2004	1000	0	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4s, v1.4s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120147	80120	40101	30018	10001	30130	30027	10003	3208665	1208738	3084304	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60288	10015	30046	40006	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10002	3211268	1209871	3086831	70107	30206	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120043	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10014	3208991	1208954	3084635	70182	30244	10015	30043	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120161	80030	40011	30018	10001	30040	30027	10003	3209032	1209391	3084574	70018	30028	10003	30009	60036	10003	30009	40001	10000	20000	40010
70025	120082	80027	40016	30010	10001	30043	30032	10000	3209312	1209461	3084834	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120082	80027	40016	30010	10001	30043	30032	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4s, v1.4s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120198	80120	40101	30018	10001	30130	30027	10003	3208839	1208797	3084467	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70205	120124	80117	40106	30010	10001	30133	30032	10003	3209033	1208990	3084673	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120154	80030	40011	30018	10001	30040	30027	10000	3209295	1209514	3084829	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208992	1209375	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120133	80029	40015	30012	10002	30043	30031	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60104	10015	30043	40006	10000	20000	40010
79537	158802	88820	44912	30045	13863	34788	30061	10003	3211263	1210165	3086633	70018	30028	10003	30009	60036	10003	30009	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.4s, v1.4s }, [x6]
  ld2r { v0.4s, v1.4s }, [x6]
  ld2r { v0.4s, v1.4s }, [x6]
  ld2r { v0.4s, v1.4s }, [x6]
  ld2r { v0.4s, v1.4s }, [x6]
  ld2r { v0.4s, v1.4s }, [x6]
  ld2r { v0.4s, v1.4s }, [x6]
  ld2r { v0.4s, v1.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240205	80166	240193	101	160072	80020	100	160034	80006	300	240034	973278	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80064	240125	101	160020	80004	100	160008	80064	300	241477	1421490	240286	200	80065	160127	200	80007	160013	1	80000	160000	100
240204	80240	240285	101	160122	80062	100	160122	80006	300	240034	1600438	240114	200	80007	160013	200	80124	160240	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80064	300	241448	1187786	240286	200	80065	160127	200	80007	160013	1	80000	160000	100
240204	80145	240209	101	160074	80034	100	160067	80006	300	240034	1600438	240114	200	80007	160013	200	80065	160127	1	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240025	80172	240103	11	160072	80020	10	160034	80006	30	240035	1216510	240024	20	80007	160013	20	80037	160071	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240018	1600496	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80034	30	240118	984576	240106	20	80035	160069	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80037	30	240126	1549740	240111	20	80037	160071	20	80000	160000	1	80000	160000	10
111203	50002	111181	2042	72074	37065	1943	72066	80000	30	240080	1600470	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240029	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10

LD2R (4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations