Icestorm: LD2R (8B) measurements

Code:

  ld2r { v0.8b, v1.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
63005	29509	3031	1	2028	1002	2004	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29290	3005	1	2004	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29303	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29301	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29305	3003	1	2002	1000	2000	1001	3038	15358	3003	1001	2002	1000	2000	1	1000	2000
63004	29309	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29286	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29305	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29311	3003	1	2002	1000	2000	1000	3000	15274	3000	1000	2000	1000	2000	1	1000	2000
63004	29354	3005	1	2004	1000	2000	1000	3006	15286	3000	1000	2000	1000	2000	1	1000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8b, v1.8b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120230	80120	40101	30018	10001	30130	30027	10014	3210433	1209473	3085999	70179	30244	10015	30045	60216	10003	30009	40001	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60290	10015	30044	40006	10000	20000	40100
70204	120072	80107	40101	30006	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70205	120075	80114	40106	30007	10001	30133	30032	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120049	80104	40101	30003	10000	30103	30002	10013	3209429	1209115	3085024	70178	30242	10015	30045	60216	10003	30009	40001	10000	20000	40100
70204	120044	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70026	120316	80040	40016	30022	10002	30070	30057	11101	3274003	1227185	3087962	73286	32886	11302	30085	60036	10003	30009	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3208917	1209365	3084470	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120075	80024	40016	30007	10001	30043	30032	10000	3209241	1209492	3084782	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8b, v1.8b }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120145	80120	40101	30018	10001	30130	30027	10003	3208854	1208808	3084479	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60284	10015	30043	40006	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3209033	1208990	3084673	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3209033	1208987	3084673	70108	30208	10003	30009	60286	10015	30046	40006	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10014	3209244	1209043	3084879	70178	30240	10015	30045	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120155	80030	40011	30018	10001	30040	30027	10003	3209069	1209462	3084619	70018	30028	10003	30009	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60036	10003	30009	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120051	80017	40011	30006	10000	30013	30002	10000	3209042	1209353	3084572	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120051	80017	40011	30006	10000	30010	30000	10014	3211262	1210313	3086722	70089	30063	10015	30046	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120050	80017	40011	30006	10000	30010	30000	10023	3212400	1210674	3087908	70159	30092	10024	30072	60308	10048	30140	40033	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240205	80178	240193	101	160072	80020	100	160034	80006	300	240035	986130	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80037	160071	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240052	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240075	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240025	80166	240106	11	160074	80021	10	160036	80006	30	240035	1088510	240024	20	80007	160013	20	80000	160000	1	80000	160000	10
240024	80071	240031	11	160020	80000	10	160000	80000	30	240248	1600538	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240025	80092	240100	11	160058	80031	10	160064	80000	30	240203	1600444	240010	20	80000	160000	20	80029	160057	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10

LD2R (8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations