Icestorm: LD2R (8H) measurements

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
63005	29620	3031	1	2028	1002	2004	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29399	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29460	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29438	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29426	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29446	3005	1	2004	1000	2000	1000	3001	15286	3000	1000	2000	1000	2000	1	1000	2000
63004	30012	3009	1	2008	1000	2000	1000	3003	15296	3000	1000	2000	1000	2000	1	1000	2000
63004	29360	3005	1	2004	1000	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29360	3005	1	2004	1000	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000
63004	29370	3005	1	2004	1000	2000	1000	3000	15290	3000	1000	2000	1000	2000	1	1000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120145	80120	40101	30018	10001	30130	30027	10003	3210837	1209583	3086388	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120043	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
48382	84016	51476	26806	15570	9100	21151	15589	16990	2475396	984276	2124883	71413	39832	18924	20769	60284	10015	30043	40006	10000	20000	40100
70204	120041	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60288	10015	30045	40006	10000	20000	40100
70204	120059	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10015	3209083	1208907	3084708	70180	30245	10015	30044	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10014	3209117	1209005	3084752	70179	30244	10015	30045	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60284	10015	30045	40006	10000	20000	40100
70204	120046	80104	40101	30003	10000	30103	30002	10014	3210437	1209532	3086030	70181	30242	10015	30043	60212	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120299	80030	40011	30018	10001	30040	30027	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120079	80026	40015	30009	10002	30043	30031	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209106	1209435	3084645	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60104	10015	30046	40006	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120154	80120	40101	30018	10001	30130	30027	10003	3208719	1208758	3084354	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60284	10015	30043	40006	10000	20000	40100
70204	120049	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120043	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10015	3209136	1209013	3084772	70180	30244	10015	30044	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208871	1208929	3084522	70108	30208	10003	30009	60286	10015	30045	40007	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120120	80104	40101	30003	10000	30103	30002	10003	3209060	1209006	3084704	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10003	3208790	1208897	3084444	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70026	120184	80039	40015	30021	10003	30070	30056	10003	3208978	1209371	3084522	70018	30028	10003	30009	60020	10000	30000	40001	10000	20000	40010
70024	120047	80017	40011	30006	10000	30010	30000	10000	3208809	1209323	3084368	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120040	80014	40011	30003	10000	30010	30000	10000	3208809	1209323	3084368	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120040	80014	40011	30003	10000	30010	30000	10000	3208809	1209323	3084368	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120040	80014	40011	30003	10000	30010	30000	10000	3208809	1209323	3084368	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120140	80024	40016	30007	10001	30043	30032	10000	3208998	1209393	3084543	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120040	80014	40011	30003	10000	30010	30000	10000	3208809	1209323	3084368	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120040	80014	40011	30003	10000	30010	30000	10000	3208809	1209323	3084368	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120040	80014	40011	30003	10000	30010	30000	10000	3208809	1209323	3084368	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120040	80014	40011	30003	10000	30010	30000	10000	3208809	1209323	3084368	70010	30020	10000	30000	60104	10015	30043	40006	10000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240205	80167	240193	101	160072	80020	100	160034	80006	300	240057	1114058	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80032	300	240334	1113006	240188	200	80033	160065	200	80007	160013	1	80000	160000	100
240205	80107	240181	101	160054	80026	100	160054	80006	300	240065	1114110	240114	200	80007	160013	200	80035	160069	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240071	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80059	240127	101	160022	80004	100	160008	80006	300	240091	1600464	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80054	240125	101	160020	80004	100	160008	80006	300	240034	1600438	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240067	1120150	240114	200	80007	160013	200	80007	160013	1	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240025	80291	240103	11	160072	80020	10	160034	80006	30	240047	1216510	240024	20	80007	160013	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240077	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80037	30	240126	1576908	240111	20	80037	160071	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80036	160070	1	80000	160000	10

LD2R (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations