Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (8H)

Test 1: uops

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630052962030311202810022004100030001528430001000200010002000110002000
630042939930051200410002000100030001528430001000200010002000110002000
630042946030051200410002000100030001528430001000200010002000110002000
630042943830051200410002000100030001528430001000200010002000110002000
630042942630051200410002000100030001528430001000200010002000110002000
630042944630051200410002000100030011528630001000200010002000110002000
630043001230091200810002000100030031529630001000200010002000110002000
630042936030051200410002000100030001529030001000200010002000110002000
630042936030051200410002000100030001529030001000200010002000110002000
630042937030051200410002000100030001529030001000200010002000110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120145801204010130018100013013030027100033210837120958330863887010830208100033000960216100033000940001100002000040100
70204120043801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
48382840165147626806155709100211511558916990247539698427621248837141339832189242076960284100153004340006100002000040100
70204120041801044010130003100003010330002100033208736120887730843947010830208100033000960288100153004540006100002000040100
70204120059801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100153209083120890730847087018030245100153004460216100033000940001100002000040100
70204120042801044010130003100003010330002100143209117120900530847527017930244100153004560216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960284100153004540006100002000040100
70204120046801044010130003100003010330002100143210437120953230860307018130242100153004360212100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120299800304001130018100013004030027100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70025120079800264001530009100023004330031100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209106120943530846457001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060104100153004640006100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120154801204010130018100013013030027100033208719120875830843547010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960284100153004340006100002000040100
70204120049801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120043801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100153209136120901330847727018030244100153004460216100033000940001100002000040100
70204120042801044010130003100003010330002100033208871120892930845227010830208100033000960286100153004540007100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100
70204120120801044010130003100003010330002100033209060120900630847047010830208100033000960216100033000940001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70026120184800394001530021100033007030056100033208978120937130845227001830028100033000960020100003000040001100002000040010
70024120047800174001130006100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70025120140800244001630007100013004330032100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060104100153004340006100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580167240193101160072800201001600348000630024005711140582401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088003230024033411130062401882008003316006520080007160013180000160000100
24020580107240181101160054800261001600548000630024006511141102401142008000716001320080035160069180000160000100
24020480054240125101160020800041001600088000630024007116004382401142008000716001320080007160013180000160000100
24020480059240127101160022800041001600088000630024009116004642401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480056240125101160020800041001600088000630024006711201502401142008000716001320080007160013180000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580291240103111600728002010160034800063024004712165102400242080007160013208000016000018000016000010
24002480056240031111600208000010160000800003024007716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800373024012615769082401112080037160071208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208003616007018000016000010