Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (post-index, 16B)

Test 1: uops

Code:

  ld2r { v0.16b, v1.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005296214033100320281002100220041000300030001536540001000200020002000100110002000
63004292954005100120041000100020001000300030001529040001000200020002000100110002000
63004293324005100120041000100020001000300030001529040001000200020002000100110002000
63004292994005100120041000100020001000300030001529040001000200020002000100110002000
63004293324005100120041000100020001000300030001529040001000200020002000100110002000
63004293474005100120041000100020001000300030001529040001000200020002000100110002000
63004292944005100120041000100020001000300030001529040001000200020002000100110002000
63004293184005100120041000100020001000300030001529040001000200020002000100110002000
63004293264005100120041000100020001000300030001529040001000200020002000100110002000
63004293124005100120041000100020001000300030001529040001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.16b, v1.16b }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512014590121501023001810001401323003310012319959994940829066938018230239100123003760216200063000950001100002000040100
7020412004090104501013000310000401043000710003319909794937829065178011430208100033000960216200063000950001100002000040100
7020412004090104501013000310000401043000710003319909794937829065178011430208100033000960216200063000950001100002000040100
7020412004090104501013000310000401043000710003319909794937829065178011430208100033000960216200063000950001100002000040100
7020412004090104501013000310000401043000710003319909794937829065178011430208100033000960216200063000950001100002000040100
7020412004090104501013000310000401043000710012319948294948029068038018230238100133003760216200063000950001100002000040100
7020412004090104501013000310000401043000710003319909794937829065178011430208100033000960216200063000950001100002000040100
7020412004090104501013000310000401043000710003319909794937829065178011430208100033000960216200063000950001100002000040100
7020412004090104501013000310000401043000710003319909794937829065178011430208100033000960216200063000950001100002000040100
7020412003090101501013000010000401043000710003319909794937829065178011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015890031500123001810001400423003110000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060096200263003750007100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000320191595050829117258001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060096200263003750007100002000040010
7002512012090038500183001910001400453003410000319991794984229098198001030020100003000060096200263003750007100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.16b, v1.16b }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2437

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512255490121501023001810001401323003210003326388196851429584688011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960278200263003750007100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326379996854629585038011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710012326440096870929590268018130238100133003760216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2917

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512327190031500123001810001400423003110003327844397307429723318002430028100033000960020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002512302390027500163001010001400453003410000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060096200243003750007100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.16b, v1.16b }, [x6], x8
  ld2r { v0.16b, v1.16b }, [x6], x8
  ld2r { v0.16b, v1.16b }, [x6], x8
  ld2r { v0.16b, v1.16b }, [x6], x8
  ld2r { v0.16b, v1.16b }, [x6], x8
  ld2r { v0.16b, v1.16b }, [x6], x8
  ld2r { v0.16b, v1.16b }, [x6], x8
  ld2r { v0.16b, v1.16b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580201320254801231601098002280123160038800353486403483121291600320235200800361600702001600181600178000680000160000100
24020480095320136801061600258000580107160010800353513873510431288604320236200800351600692001600121600108000480000160000100
24020480102320140801071600278000680108160012800073329723326441279668320124200800071600132001600141600138000580000160000100
24020480095320134801051600258000480107160010800073353543350181287288320124200800071600132001600141600138000680000160000100
24020480095320133801051600248000480107160010800073368393365001287645320124200800071600132001600141600138000580000160000100
24020480095320136801061600258000580107160010800073366313363061280797320124200800071600132001600161600168000680000160000100
24020480095320134801051600258000480107160010800073335753332481279738320124200800071600132001600141600138000680000160000100
24020480095320137801061600268000580108160012800073360383357041273744320124200800071600132001600141600138000680000160000100
24020480094320129801041600228000380106160008800373509323505841283586320241200800371600712001600141600138000580000160000100
24020480095320136801061600258000580107160010800073349263345921276064320124200800071600132001600121600108000480000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580156320153800311601028002080033160036800003800583800281376392320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003273883273631576465320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003241213240981576781320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003279243279031576669320010208000016000020160000160000800018000016000010
24002480075320041800111600308000080010160000800003031453034671600464320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003243563243331576489320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003292753292521576797320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003279583279341568943320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003232613232391569207320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003260023259801565779320010208000016000020160000160000800018000016000010