Icestorm: LD2R (post-index, 1D) measurements

Code:

  ld2r { v0.1d, v1.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
63005	29525	4033	1003	2028	1002	1002	2004	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29340	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29302	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29301	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29319	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29301	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29304	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29317	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29301	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000
63004	29301	4005	1001	2004	1000	1000	2000	1000	3000	3000	15290	4000	1000	2000	2000	2000	1001	1000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.1d, v1.1d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120154	90121	50102	30018	10001	40132	30032	10003	3199179	949294	2906395	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	120047	90107	50101	30006	10000	40104	30007	10003	3199286	949434	2906692	80114	30208	10003	30009	60278	20026	30037	50007	10000	20000	40100
70204	120047	90107	50101	30006	10000	40104	30007	10003	3199286	949434	2906692	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	120047	90107	50101	30006	10000	40104	30007	10003	3199286	949434	2906692	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	120047	90107	50101	30006	10000	40104	30007	10003	3199286	949434	2906692	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	120047	90107	50101	30006	10000	40104	30007	10003	3199286	949434	2906692	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	120120	90107	50101	30006	10000	40104	30008	10003	3199475	949495	2906872	80114	30208	10003	30009	60278	20024	30037	50008	10000	20000	40100
70204	120047	90107	50101	30006	10000	40104	30007	10003	3199286	949434	2906692	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	120047	90107	50101	30006	10000	40104	30007	10003	3199286	949434	2906692	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	120047	90107	50101	30006	10000	40104	30007	10003	3199286	949434	2906692	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120148	90031	50012	30018	10001	40042	30031	10000	3199304	949587	2909130	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	120040	90014	50011	30003	10000	40010	30000	10000	3199161	949597	2909107	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	120040	90014	50011	30003	10000	40010	30000	10000	3199161	949597	2909107	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	120040	90014	50011	30003	10000	40010	30000	10000	3199161	949597	2909107	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70025	120098	90035	50018	30016	10001	40045	30035	10000	3199539	949723	2909464	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	120040	90014	50011	30003	10000	40010	30000	10000	3199161	949597	2909107	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	120040	90014	50011	30003	10000	40010	30000	10000	3199161	949597	2909107	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	120040	90014	50011	30003	10000	40010	30000	10000	3199161	949597	2909107	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	120040	90014	50011	30003	10000	40010	30000	10000	3199161	949597	2909107	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70025	120092	90032	50018	30013	10001	40041	30027	10000	3199161	949597	2909107	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.1d, v1.1d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2444

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	122550	90121	50102	30018	10001	40132	30032	10003	3264066	968515	2958522	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	122444	90107	50101	30006	10000	40104	30007	10003	3263961	968593	2958653	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70205	122465	90118	50107	30010	10001	40135	30035	10003	3263961	968593	2958653	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	122437	90104	50101	30003	10000	40104	30007	10003	3263961	968593	2958653	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	122444	90107	50101	30006	10000	40104	30007	10003	3263961	968593	2958653	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	122444	90107	50101	30006	10000	40104	30007	10003	3263961	968593	2958653	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	122444	90107	50101	30006	10000	40104	30007	10003	3263772	968537	2958478	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	122495	90107	50101	30006	10000	40104	30007	10003	3263961	968593	2958653	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	122444	90107	50101	30006	10000	40104	30007	10003	3263961	968593	2958653	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100
70204	122444	90107	50101	30006	10000	40104	30007	10003	3263961	968593	2958653	80114	30208	10003	30009	60216	20006	30009	50001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2915

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	123130	90031	50012	30018	10001	40042	30031	10003	3279520	973392	2973318	80023	30028	10003	30009	60020	20000	30000	50001	10000	20000	40010
70024	122915	90017	50011	30006	10000	40010	30000	10000	3276774	972591	2970799	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	122915	90017	50011	30006	10000	40010	30000	10000	3276774	972591	2970799	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	122915	90017	50011	30006	10000	40010	30000	10000	3276774	972591	2970799	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	122915	90017	50011	30006	10000	40010	30000	10009	3283369	974533	2976881	80078	30050	10010	30028	60020	20000	30000	50001	10000	20000	40010
70024	122915	90017	50011	30006	10000	40010	30000	10000	3276774	972591	2970799	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	122915	90017	50011	30006	10000	40010	30000	10000	3276774	972591	2970799	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	122915	90017	50011	30006	10000	40010	30000	10000	3276774	972591	2970799	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70024	122915	90017	50011	30006	10000	40010	30000	10000	3276774	972591	2970799	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010
70025	123017	90031	50017	30013	10001	40045	30034	10000	3277125	972709	2971132	80010	30020	10000	30000	60020	20000	30000	50001	10000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240205	80220	320249	80121	160108	80020	80122	160036	80008	352122	351773	1261953	320128	200	80009	160017	200	160018	160017	80006	80000	160000	100
240204	80106	320146	80106	160035	80005	80107	160010	80006	335991	335658	1268226	320120	200	80006	160010	200	160016	160016	80006	80000	160000	100
240204	80106	320147	80106	160036	80005	80108	160012	80008	335488	335162	1270862	320128	200	80008	160016	200	160014	160013	80005	80000	160000	100
240204	80106	320142	80105	160033	80004	80107	160009	80008	335488	335162	1270862	320128	200	80008	160016	200	160016	160016	80006	80000	160000	100
240204	80106	320147	80106	160036	80005	80108	160012	80006	329600	331031	1362549	320120	200	80006	160010	200	160012	160010	80005	80000	160000	100
240204	80106	320144	80105	160035	80004	80107	160010	80035	349202	348854	1274982	320236	200	80035	160069	200	160014	160013	80006	80000	160000	100
240204	80106	320145	80105	160036	80004	80107	160010	80008	336154	335821	1271010	320128	200	80008	160016	200	160016	160016	80006	80000	160000	100
240204	80106	320146	80106	160035	80005	80107	160010	80007	332708	332372	1271358	320124	200	80007	160013	200	160014	160013	80005	80000	160000	100
240204	80106	320147	80106	160036	80005	80108	160012	80008	335488	335162	1270862	320128	200	80008	160016	200	160012	160010	80005	80000	160000	100
240204	80106	320146	80106	160035	80005	80107	160010	80006	333760	333431	1272681	320120	200	80006	160010	200	160014	160013	80006	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240025	80168	320161	80032	160108	80021	80034	160038	80008	329943	329919	1554943	320038	20	80008	160016	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80034	386506	386474	1351482	320142	20	80035	160069	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80000	327332	327306	1600192	320010	20	80000	160000	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80000	329918	329892	1600192	320010	20	80000	160000	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80000	320081	320056	1600192	320010	20	80000	160000	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80000	327011	326985	1600192	320010	20	80000	160000	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80000	320081	320056	1600192	320010	20	80000	160000	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80000	319997	319971	1600192	320010	20	80000	160000	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80034	387514	387482	1347450	320142	20	80035	160069	20	160000	160000	80001	80000	160000	10
240024	80046	320031	80011	160020	80000	80010	160000	80000	329918	329892	1600192	320010	20	80000	160000	20	160000	160000	80001	80000	160000	10

LD2R (post-index, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations