Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (post-index, 2D)

Test 1: uops

Code:

  ld2r { v0.2d, v1.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005294444033100320281002100220041000300030001529040001000200020002000100110002000
63004293624005100120041000100020001000300030001529040001000200020002000100110002000
63004293844005100120041000100020001000300030001529040001000200020002000100110002000
63004293574005100120041000100020001000300030001529040001000200020002000100110002000
63004293634005100120041000100020001000300030001529040001000200020002000100110002000
63004293624005100120041000100020001000300030001529040001000200020002000100110002000
63004293574005100120041000100020001000300030001529040001000200020002000100110002000
63004293764005100120041000100020001000300030001529040001000200020002000100110002000
63004293814005100120041000100020001000300030001529040001000200020002000100110002000
63004293344005100120041000100020001000300030001529040001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2d, v1.2d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015090121501023001810001401323003210003319904094925129062528011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960278200243003750007100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004390104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960276200243003750008100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015490031500123001810001400423003210000319930494958729091308001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000320245595068829122428001030020100003000060256200723011250041100002000040010
7002512010490032500183001310001400453003510000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004890017500113000610000400103000010000319967494976129095918001030020100003000060200200543008450031100002000040010
7002412004890017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002512009190031500173001310001400453003510000319935094965329092828001030020100003000060020200003000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2d, v1.2d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2437

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020612256590132501083002210002401633006010003326385596850729584238011430208100033000960216200063000950001100002000040100
7020412244490104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020512255290124501073001610001401353003510003326379996854529585038011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960276200263003750007100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2915

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002612318890045500183002510002400733006110003328218397418829757938002330028100033000960020200003000050001100002000040010
7002412291590017500113000610000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002512297890029500183001010001400473003610000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327658597253529706248001030020100003000060096200263003750007100002000040010
7002412291590017500113000610000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002512307790028500173001010001400453003510000327658597253529706248001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0013

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580208320251801221601088002180123160036800083606093602711278275320128200800091600172001600181600178000780000160000100
24020480091320121801041600148000380106160008800373479603476191275010320242200800371600712001600121600108000480000160000100
24020480104320146801061600358000580107160010800083344553341211271456320128200800081600162001600161600168000680000160000100
24020480104320147801061600368000580108160012800073416763413451276323320124200800071600132001600161600168000680000160000100
24020480104320146801061600358000580107160010800073364583361271277246320124200800071600132001600141600138000580000160000100
24020480104320147801061600368000580108160012800073343903340591274972320124200800071600132001600141600138000580000160000100
24020480104320144801051600358000480107160010800073327493324291264798320124200800071600132001600141600138000680000160000100
24020480104320144801051600358000480107160010800083344083340781267654320128200800081600162001600141600138000680000160000100
24020480104320144801051600358000480107160010800353471723468341270844320237200800351600692001600121600108000480000160000100
24020480104320147801061600368000580108160012800073245683262331430764320124200800071600132001600121600108000580000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580167320165800331601108002280035160040800003800583802661492734320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003200283200031600192320010208000016000020160000160000800018000016000010
24002480060320031800111600208000080010160000800003044993047571600226320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003256013255761600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003216603216331600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003315703315421600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003315703315421600192320010208000016000020160000160000800018000016000010
24002580112320175800451600968003480047160067800003199973199711600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003299183298921600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003266513266241587506320010208000016000020160000160000800018000016000010