Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (post-index, 2S)

Test 1: uops

Code:

  ld2r { v0.2s, v1.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005295664033100320281002100220041000300030001527040001000200020002000100110002000
63004293964003100120021000100020001000300030001527040001000200020002000100110002000
63005294484009100220061001100120021000300030001527040001000200020002000100110002000
63004294604003100120021000100020001000300030001527840001000200020002000100110002000
63004294234003100120021000100020001000300030001527040001000200020002000100110002000
63004293524003100120021000100020001000300030231531640001000200020002000100110002000
63004295184003100120021000100020001000300030011527440001000200020002000100110002000
63004296624003100120021000100020001000300030001527040001000200020002000100110002000
63004294234003100120021000100020001000300030001527040001000200020002000100110002000
63004293704003100120021000100020001000300030001527040001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2s, v1.2s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015590121501023001810001401323003210003319923394936429065298011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020512008890122501083001310001401353003510003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020512011890121501073001310001401353003510003319928694943429066928011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512014690031500123001810001400423003310000319930494958729091308001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002512008190029500183001010001400453003410000319930594958729093078001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002512008090028500173001010001400453003510000319978294979729096928001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2s, v1.2s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2435

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512268690121501023001810001401323003210003326382796849829584188011430208100033000960216200063000950001100002000040100
7020512250990115501073000710001401353003510003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412243590104501013000310000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412243590104501013000310000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412243590104501013000310000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412243590104501013000310000401043000710003326371896852129584288011430208100033000960280200283003750007100002000040100
7020412243590104501013000310000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412243590104501013000310000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412243590104501013000310000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412243590104501013000310000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2908

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512312390031500123001810001400423003110000327677497259129707998001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327971797357529736078001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002512302790025500173000710001400453003410000327658597253529706248001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580218320250801221601078002180123160036800083490623487271255680320128200800091600172001600181600178000780000160000100
24020480102320140801071600278000680108160012800073357423354121283760320124200800071600132001600141600138000580000160000100
24020480094320132801051600238000480106160008800073371263368011284055320124200800071600132001600141600138000680000160000100
24020480095320136801061600258000580107160010800073342163338871279822320124200800071600132001600141600138000680000160000100
24020580136320254801361600838003580138160070800073360163356931280339320124200800071600132001600161600168000680000160000100
24020480095320134801051600258000480107160010800073366313363061280797320124200800071600132001600161600168000680000160000100
24020480095320134801051600258000480107160010800073366313363061280797320124200800071600132001600141600138000680000160000100
24020480095320134801051600258000480107160010800073348623345391279725320124200800071600132001600141600138000580000160000100
24020480094320129801041600228000380106160008800073366313363061280797320124200800071600132001600161600168000680000160000100
24020480095320135801051600268000480107160010800073342683339321279517320124200800071600132001600161600168000680000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580188320153800301601048001980032160034800093801003800701376488320042208000916001720160000160000800018000016000010
24002480054320041800111600308000080010160000800003315993315751568647320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003414543414301518342320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003430283430051571871320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003430283430051571871320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800363843843843651360160320150208003616007220160000160000800018000016000010
24002480054320041800111600308000080010160000800003333243332991571267320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003439223438981563415320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003234593234371556219320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003324073323831568543320010208000016000020160000160000800018000016000010