Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (post-index, 4H)

Test 1: uops

Code:

  ld2r { v0.4h, v1.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005296544033100320281002100220041000300030001528440001000200020002000100110002000
63004293774003100120021000100020001000300030001527040001000200020002000100110002000
63004293944005100120041000100020001000300030001527040001000200020002000100110002000
63004293994003100120021000100020001000300030001527040001000200020002000100110002000
63004293684003100120021000100020001000300030001527040001000200020002000100110002000
63004293934003100120021000100020001000300030001527040001000200020002000100110002000
63004293944005100120041000100020001000300030001527040001000200020002000100110002000
63004293944003100120021000100020001000300030001527040001000200020002000100110002000
63004293444003100120021000100020001000300030001527040001000200020002000100110002000
63004293544003100120021000100020001000300030001527040001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4h, v1.4h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512014890121501023001810001401323003210003319909794932429064058011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960278200263003750008100002000040100
7020412005890104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960274200243003750007100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015290031500123001810001400423003210003319932694963529092458002430028100033000960036200063000950001100002000040010
7002412004090014500113000310000400103000010012319959494975529094968009230059100123003760020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010012319957694975329095388009130058100133003760020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4h, v1.4h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2442

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512255290121501023001810001401323003310003326421296850529585248011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710012326560496911429599708018330239100143003960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412245090107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020512247290118501073001010001401353003510003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2915

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512313090031500123001810001400423003110003327957497340829733688002330028100033000960020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002512297890028500173001010001400453003610000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412290590014500113000310000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060096200263003750006100002000040010
7002412292690017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580215320248801211601078002080123160036800083570703567201264514320128200800081600142001600141600138000580000160000100
24020480102320140801071600278000680108160012800073334023330761277016320124200800071600132001600161600168000680000160000100
24020480095320134801051600258000480107160010800353350913347601292099320236200800351600692001600121600108000480000160000100
24020480095320137801061600268000580108160012800073335573332211272534320124200800071600132001600141600138000580000160000100
24020480094320132801051600238000480106160008800073329723326441279668320124200800071600132001600141600138000580000160000100
24020480095320134801051600258000480107160010800073360383357041273744320124200800071600132001600141600138000580000160000100
24020480094320129801041600228000380106160008800073366313363061280797320124200800071600132001600161600168000680000160000100
24020480095320136801061600258000580107160010800073366313363061280797320124200800071600132001600161600168000680000160000100
24020480094320129801041600228000380106160008800073333363330071274019320124200800071600132001600121600108000580000160000100
24020480095320137801061600268000580108160012800363277373284771336316320240200800361600712001600141600138000580000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580300320154800311601038002080032160035800093640963640691440540320042208000916001720160000160000800018000016000010
24002480056320041800111600308000080010160000800003302393302161576347320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003269433269201568233320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003379983379731570687320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003308233308011568707320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003302193301941570991320010208000016000020160076160074800358000016000010
24002480056320041800111600308000080010160000800003379983379731570687320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003229143228901559881320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003080583097561601078320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003270713270471568963320010208000016000020160000160000800018000016000010