Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (post-index, 4S)

Test 1: uops

Code:

  ld2r { v0.4s, v1.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63006297484035100320301002100220041000300030001527040001000200020002000100110002000
63004294274003100120021000100020001000300030001527040001000200020002000100110002000
63004294424003100120021000100020001000300030001527040001000200020002000100110002000
63004294004003100120021000100020001000300030001527040001000200020002000100110002000
63004294164003100120021000100020001000300030001527040001000200020002000100110002000
63004294154003100120021000100020001000300030001527040001000200020002000100110002000
63004294154003100120021000100020001000300030001527040001000200020002000100110002000
63004294064003100120021000100020001000300030001527040001000200020002000100110002000
63004294084003100120021000100020001000300030001527040001000200020002000100110002000
63004294174003100120021000100020001000300030001527040001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4s, v1.4s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015490121501023001810001401323003210003319912294922129062118011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960276200263003750007100002000040100
7020412013490107501013000610000401043000710003319982694961229072108011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710012319965294952929069678018330239100143003760216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015490031500123001810001400423003210000319930494958729091308001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060096200263003750007100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060098200243003750008100002000040010
7002412005190017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4s, v1.4s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2437

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512255490121501023001810001401323003210003326427696858329586988011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710012326388396855629585168018230238100133003760216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020512246790114501063000710001401353003310003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2917

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512325490031500123001810001400423003110003327841697306629723068002430028100033000960020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002512317290028500173001010001400453003510000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002512301490027500163001010001400453003210000327731497277029713138001030020100003000060096200263003750007100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412300490017500113000610000400103000010000327693697264329709538001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0013

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580224320250801221601078002180123160036800083303563317431391645320129200800081600142001600181600178000780000160000100
24020480117320147801061600368000580106160010800063315833312551271470320120200800061600102001600161600168000680000160000100
24020580156320260801351600918003480137160068800073343903340581275024320124200800071600132001600141600138000580000160000100
24020480106320144801051600358000480107160010800073333333330031265298320124200800071600132001600141600138000580000160000100
24020480106320144801051600358000480107160010800073357893354521271226320124200800071600132001600141600138000580000160000100
24020480106320144801051600358000480107160010800073348233344961276395320124200800071600132001600141600138000580000160000100
24020480106320146801061600358000580107160010800073364583361261277298320124200800071600132001600141600138000580000160000100
24020480106320147801061600368000580108160012800073334773331831278097320124200800071600132001600141600138000680000160000100
24020480106320144801051600358000480107160010800073366653363361263497320124200800071600132001600161600168000680000160000100
24020580149320265801361600948003580138160071800073312483310051290654320124200800071600132001600761600748003680000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580169320153800311601028002080033160036800003800583800281376392320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003247393247181576569320010208000016000020160072160072800348000016000010
24002480060320041800111600308000080010160000800003279583279341568943320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003234593234371556219320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003447443447211568907320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003436343436091572531320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003430283430051571871320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003445223444991569887320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003228833228611565753320010208000016000020160072160072800348000016000010
24002480054320041800111600308000080010160000800003322703322481577041320010208000016000020160000160000800018000016000010