Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (post-index, 8B)

Test 1: uops

Code:

  ld2r { v0.8b, v1.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005298104069100720561006100620121000300030001528440001000200020002000100110002000
63004293814005100120041000100020001000300030001528440001000200020002000100110002000
63004293994005100120041000100020001000300030001528440001000200020002000100110002000
63004293794005100120041000100020001000300030001528440001000200020002000100110002000
63004294304005100120041000100020001000300030001528440001000200020002000100110002000
63004294004005100120041000100020001000300030001528440001000200020002000100110002000
63004294094005100120041000100020001000300030001528440001000200020002000100110002000
63004293784005100120041000100020001000300030001528440001000200020002000100110002000
63004293784005100120041000100020001000300030001528440001000200020002000100110002000
63004294304005100120041000100020001000300030001528440001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8b, v1.8b }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015490121501023001810001401323003210003319947294937929066528011430208100033000960216200063000950001100002000040100
7020512008190119501083001010001401353003410003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319958394952229069678011430208100033000960216200063000950001100002000040100
7020512008190121501103001010001401373003610003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412005890107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412014990107501013000610000401043000710003320085294990229081428011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015090031500123001810001400423003110000319940494966929093848001030020100003000060020200003000050001100002000040010
7002412005490014500113000310000400103000010000319921594961329091578001030020100003000060020200003000050001100002000040010
7002412004290014500113000310000400103000010000319921594961329091578001030020100003000060020200003000050001100002000040010
7002412004290014500113000310000400103000010000319921594961329091578001030020100003000060020200003000050001100002000040010
7002412004290014500113000310000400103000010000319921594961329091578001030020100003000060020200003000050001100002000040010
7002412004290014500113000310000400103000010000319921594961329091578001030020100003000060098200263003750008100002000040010
7002412004690014500113000310000400103000010000319921594961329091578001030020100003000060020200003000050001100002000040010
7002412004290014500113000310000400103000010000319921594961329091578001030020100003000060020200003000050001100002000040010
7002412004290014500113000310000400103000010000319921594961329091578001030020100003000060020200003000050001100002000040010
7002412004290014500113000310000400103000010000319921594961329091578001030020100003000060020200003000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8b, v1.8b }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2444

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512269690121501023001810001401323003210003326411696858329586788011430208100033000960216200063000950001100002000040100
7020412244490107501013000610000401043000710003326396196859329586538011430208100033000960216200063000950001100002000040100
7020412244490107501013000610000401043000710003326396196859329586538011430208100033000960276200243003750007100002000040100
7020412244490107501013000610000401043000710003326396196859329586538011430208100033000960216200063000950001100002000040100
7020412244490107501013000610000401043000710003326396196859329586538011430208100033000960216200063000950001100002000040100
7020412244490107501013000610000401043000710003326396196859329586538011430208100033000960216200063000950001100002000040100
7020412244490107501013000610000401043000710003326396196859329586538011430208100033000960216200063000950001100002000040100
7020412244490107501013000610000401043000710012326451796869329590328018130238100123003760216200063000950001100002000040100
7020412244490107501013000610000401043000710003326396196859329586538011430208100033000960216200063000950001100002000040100
7020412244490107501013000610000401043000710003326396196859329586538011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2915

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512313090031500123001810001400423003110003327836297305029722568002430028100033000960020200003000050001100002000040010
7002512290590027500163001010001400453003410000328066197369429742708001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060096200263003750007100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200003000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.8b, v1.8b }, [x6], x8
  ld2r { v0.8b, v1.8b }, [x6], x8
  ld2r { v0.8b, v1.8b }, [x6], x8
  ld2r { v0.8b, v1.8b }, [x6], x8
  ld2r { v0.8b, v1.8b }, [x6], x8
  ld2r { v0.8b, v1.8b }, [x6], x8
  ld2r { v0.8b, v1.8b }, [x6], x8
  ld2r { v0.8b, v1.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0013

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580214320251801221601088002180123160036800063609523605951269147320122200800061600122001600181600178000680000160000100
24020480106320147801061600368000580108160012800083360483357171270402320128200800081600162001600141600138000680000160000100
24020480106320144801051600358000480107160010800073324283321061268383320124200800071600132001600121600108000580000160000100
24020480106320146801061600358000580107160010800073376993373741277984320124200800071600132001600141600138000580000160000100
24020480106320146801061600358000580107160010800073324153320821267886320124200800071600132001600141600138000580000160000100
24020480106320147801061600368000580108160012800083369333366051275191320128200800081600162001600761600748003680000160000100
24020480106320147801061600368000580108160012800083308783305521269640320128200800081600162001600141600138000580000160000100
24020480106320144801051600358000480107160010800073340233337421268230320124200800071600132001600161600168000680000160000100
24020480106320146801061600358000580107160010800073359503356251276515320124200800071600132001600141600138000680000160000100
24020480106320147801061600368000580107160010800083338013334681274639320128200800081600162001600161600168000680000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580156320157800311601068002080033160036800003800583800281376392320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003322703322481577041320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003234593234371556219320010208000016000020160000160000800018000016000010
24002580111320169800441600928003380046160068800003276943278871568519320010208000016000020160000160000800018000016000010
24002480054320041800111600308000080010160000800003324073323831568543320010208000016000020160000160000800018000016000010
24002580112320167800441600908003380046160068800003013393017011600460320010208000016000020160016160016800068000016000010
24002480063320041800111600308000080010160000800003439223438971563467320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003299773299521568691320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003234593234361556271320010208000016000020160000160000800018000016000010
24002480056320041800111600308000080010160000800003390543390281557407320010208000016000020160000160000800018000016000010