Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (post-index, 8H)

Test 1: uops

Code:

  ld2r { v0.8h, v1.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005295774033100320281002100220041000300030001527440001000200020002000100110002000
63004296674003100120021000100020001000300030031528040001000200020002000100110002000
63004300024011100320061002100220041000300030001527640001000200020002000100110002000
63004298224003100120021000100020001000300030001527440001000200020002000100110002000
63004293234003100120021000100020001000300030001527440001000200020002000100110002000
63004293034003100120021000100020001000300030001527440001000200020002000100110002000
63004297274003100120021000100020001000300030001527440001000200020002000100110002000
63004293254003100120021000100020001000300030001527440001000200020002000100110002000
63004293014003100120021000100020001000300030001527440001000200020002000100110002000
63004293364003100120021000100020001000300030001527440001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8h, v1.8h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015690121501023001810001401323003310003319922994930729064258011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960276200263003750007100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960280200283003850009100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512014790031500123001810001400423003110000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010012319955794974629094638009030057100123003760020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010012319957294975029095978009130058100133003760020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8h, v1.8h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2444

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512254590121501023001810001401323003210003326397796849029584328011530209100043000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960276200263003750006100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326410196857829586508011430208100033000960216200063000950001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100
7020412244490104501013000310000401043000710003326377296853729584788011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2917

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512326990031500123001810001400423003110000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010012328064497376729744128009230059100123003760020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002512297490028500173001010001400453003410000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2r { v0.8h, v1.8h }, [x6], x8
  ld2r { v0.8h, v1.8h }, [x6], x8
  ld2r { v0.8h, v1.8h }, [x6], x8
  ld2r { v0.8h, v1.8h }, [x6], x8
  ld2r { v0.8h, v1.8h }, [x6], x8
  ld2r { v0.8h, v1.8h }, [x6], x8
  ld2r { v0.8h, v1.8h }, [x6], x8
  ld2r { v0.8h, v1.8h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580206320248801211601078002080123160036800063546103542571255116320122200800061600122001600181600178000780000160000100
24020480098320141801061600308000580107160010800083361053357731270385320128200800081600162001600121600108000480000160000100
24020480103320137801051600288000480106160010800073327083323711271142320124200800071600132001600141600138000580000160000100
24020480098320141801061600308000580108160012800073379173375911283009320124200800071600132001600161600168000680000160000100
24020480098320141801061600308000580108160012800073382953379611273142320124200800071600132001600121600108000580000160000100
24020580136320252801341600858003380135160066800073320983317771269272320124200800071600132001600141600138000680000160000100
24020480098320139801051600308000480107160010800083344553341191271292320128200800081600162001600141600138000580000160000100
24020480098320138801051600298000480107160010800083408703405371279001320128200800081600162001600141600138000680000160000100
24020480097320133801041600268000380106160008800073327083323711271142320124200800071600132001600161600168000680000160000100
24020480098320141801061600308000580108160012800073352993349651272176320123200800071600132001600161600168000680000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580165320151800301601028001980032160034800094040904040621312540320042208000916001720160000160000800018000016000010
24002480048320035800111600248000080010160000800003342983342731570223320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003445223444971569723320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003213953213711558441320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003237403237151568683320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003378003377771574447320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003213953213711558441320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003240403240141559119320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003302393302151576131320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003361713361451576499320010208000016000020160000160000800018000016000010