Icestorm: LD2 (multiple, 16B) measurements

Code:

  ld2 { v0.16b, v1.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.004

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	30603	4033	1	2028	2004	2004	2000	6000	15289	4000	2000	2000	2000	4000	1	2000	2000
64004	31259	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29510	4005	1	2004	2000	2000	2000	6000	15285	4000	2000	2000	2000	4000	1	2000	2000
64004	29484	4005	1	2004	2000	2000	2000	6000	15285	4000	2000	2000	2000	4000	1	2000	2000
64004	29496	4005	1	2004	2000	2000	2000	6000	15285	4000	2000	2000	2000	4000	1	2000	2000
64004	29515	4005	1	2004	2000	2000	2000	6000	15285	4000	2000	2000	2000	4000	1	2000	2000
64004	29495	4005	1	2004	2000	2000	2000	6000	15285	4000	2000	2000	2000	4000	1	2000	2000
64004	29504	4005	1	2004	2000	2000	2000	6000	15285	4000	2000	2000	2000	4000	1	2000	2000
64004	29514	4005	1	2004	2000	2000	2000	6000	15285	4000	2000	2000	2000	4000	1	2000	2000
64004	29508	4005	1	2004	2000	2000	2000	6000	15285	4000	2000	2000	2000	4000	1	2000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.16b, v1.16b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0044

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120158	90121	40101	30018	20002	30130	30024	20004	3208952	2139188	3084536	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208719	2139004	3084332	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208763	2139076	3084382	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208763	2139076	3084382	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20024	3209057	2139254	3084638	80189	30242	20026	30040	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208763	2139076	3084382	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120130	90107	40101	30006	20000	30103	30002	20004	3209357	2139458	3084926	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208925	2139184	3084538	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208871	2139148	3084486	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80205	120134	90115	40106	30007	20002	30133	30032	20024	3209031	2139240	3084618	80189	30242	20026	30040	60218	20006	50015	40001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120515	90031	40011	30018	20002	30040	30024	20000	3208930	2139042	3084418	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60104	20026	50066	40006	20000	20000	40010
80024	120048	90017	40011	30006	20000	30013	30002	20000	3208741	2138930	3084264	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120042	90014	40011	30003	20000	30010	30000	20000	3208860	2139050	3084387	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80025	120110	90025	40016	30007	20002	30043	30032	20000	3208833	2139028	3084353	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.16b, v1.16b }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80206	120188	90132	40106	30022	20004	30160	30054	20004	3208941	2139144	3084525	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60284	20030	50074	40005	20000	20000	40100
80204	120050	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60284	20026	50066	40006	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120189	90031	40011	30018	20002	30040	30024	20004	3208758	2138974	3084291	80019	30029	20006	30009	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20024	3209093	2139222	3084594	80099	30062	20026	30040	60020	20000	50000	40001	20000	20000	40010
80025	120073	90025	40016	30007	20002	30043	30032	20000	3208806	2139012	3084331	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120042	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60104	20026	50066	40006	20000	20000	40010
80024	120058	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120044	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120042	90014	40011	30003	20000	30010	30000	20000	3209103	2139212	3084621	80010	30020	20000	30000	60086	20020	50051	40009	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.16b, v1.16b }, [x6]
  ld2 { v0.16b, v1.16b }, [x6]
  ld2 { v0.16b, v1.16b }, [x6]
  ld2 { v0.16b, v1.16b }, [x6]
  ld2 { v0.16b, v1.16b }, [x6]
  ld2 { v0.16b, v1.16b }, [x6]
  ld2 { v0.16b, v1.16b }, [x6]
  ld2 { v0.16b, v1.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0020

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	80263	320267	101	160128	160038	100	160038	160012	300	480272	1282096	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80171	320153	101	160044	160008	100	160012	160012	300	480272	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320205	80218	320213	101	160074	160038	100	160054	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	494730	1296426	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	491490	1293304	320124	200	160012	160012	200	160012	320024	1	160000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	80509	320175	11	160126	160038	10	160038	160000	30	671010	1471176	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320025	80116	320109	11	160060	160038	10	160054	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80062	320035	11	160024	160000	10	160000	160000	30	536128	1336388	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
356019	196000	352958	19301	160188	173469	19273	160116	160000	30	597122	1413432	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80061	320037	11	160026	160000	10	160000	160000	30	574130	1374398	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10

LD2 (multiple, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations