Icestorm: LD2 (multiple, 2D) measurements

Code:

  ld2 { v0.2d, v1.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.004

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	29827	4033	1	2028	2004	2004	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29653	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29603	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29640	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29969	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29641	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29605	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29606	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29826	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	30305	4005	1	2004	2000	2000	2000	6000	15292	4000	2000	2000	2000	4000	1	2000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2d, v1.2d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120147	90121	40101	30018	20002	30130	30024	20024	3209249	2139370	3084797	80189	30241	20026	30039	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208719	2139004	3084332	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208763	2139076	3084382	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20024	3209035	2139242	3084623	80191	30241	20026	30039	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208763	2139076	3084382	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80205	120075	90115	40106	30007	20002	30133	30032	20004	3208898	2139166	3084512	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208817	2139112	3084434	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120045	90104	40101	30003	20000	30103	30002	20004	3210572	2140264	3086088	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120045	90104	40101	30003	20000	30103	30002	20004	3208763	2139076	3084382	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208763	2139076	3084382	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120156	90031	40011	30018	20002	30040	30024	20000	3208930	2139042	3084418	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80025	120090	90031	40016	30013	20002	30043	30032	20000	3210291	2139942	3085641	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20024	3209282	2139334	3084750	80099	30062	20026	30040	60020	20000	50000	40001	20000	20000	40010
80024	120051	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80025	120127	90031	40016	30013	20002	30040	30030	20004	3209039	2139184	3084534	80019	30029	20006	30009	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2d, v1.2d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120150	90121	40101	30018	20002	30130	30024	20004	3208908	2139116	3084486	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120042	90104	40101	30003	20000	30103	30002	20004	3208952	2139188	3084536	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120049	90107	40101	30006	20000	30103	30002	20024	3209060	2139258	3084642	80189	30242	20026	30040	60218	20006	50015	40001	20000	20000	40100
80204	120049	90107	40101	30006	20000	30103	30002	20004	3208763	2139076	3084382	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208854	2139084	3084442	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80206	120167	90132	40111	30017	20004	30163	30062	20004	3208854	2139084	3084442	80109	30209	20006	30009	60284	20026	50066	40006	20000	20000	40100
80204	120061	90107	40101	30006	20000	30103	30002	20004	3208952	2139192	3084544	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120050	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120148	90031	40011	30018	20002	30040	30024	20004	3209066	2139202	3084560	80019	30029	20006	30009	60038	20006	50015	40001	20000	20000	40010
80024	120055	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120050	90017	40011	30006	20000	30010	30000	20000	3209076	2139176	3084559	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60104	20026	50066	40006	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120049	90017	40011	30006	20000	30010	30000	20000	3209022	2139140	3084507	80010	30020	20000	30000	60038	20006	50015	40001	20000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0019

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	80291	320267	101	160128	160038	100	160038	160012	300	480210	1280228	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80150	320135	101	160026	160008	100	160012	160012	300	480210	1280222	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80150	320135	101	160026	160008	100	160012	160012	300	480210	1280222	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80150	320135	101	160026	160008	100	160012	160012	300	480210	1280222	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80150	320135	101	160026	160008	100	160012	160012	300	480210	1280222	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80150	320135	101	160026	160008	100	160012	160012	300	480210	1280222	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320205	80207	320201	101	160062	160038	100	160054	160012	300	515826	1315722	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80150	320135	101	160026	160008	100	160012	160012	300	480210	1280222	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80172	320135	101	160026	160008	100	160012	160012	300	480210	1280222	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80150	320135	101	160026	160008	100	160012	160012	300	480210	1280222	320124	200	160012	160012	200	160012	320024	1	160000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	80250	320177	11	160128	160038	10	160038	160012	30	480146	1296444	320034	20	160012	160012	20	160000	320000	1	160000	160000	10
320024	80071	320035	11	160024	160000	10	160000	160000	30	552224	1352436	320010	20	160000	160000	20	160054	320108	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80065	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160054	320108	1	160000	160000	10
320024	80058	320035	11	160024	160000	10	160000	160000	30	480140	1280408	320010	20	160000	160000	20	160000	320000	1	160000	160000	10

LD2 (multiple, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations