Icestorm: LD2 (multiple, 2S) measurements

Code:

  ld2 { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
63005	29730	3031	1	2028	1002	2004	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29418	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29404	3005	1	2004	1000	2000	1001	3001	15286	3001	1001	2000	1000	2000	1	1000	2000
63004	29400	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29397	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29407	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29397	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	30116	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	30302	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000
63004	29560	3005	1	2004	1000	2000	1000	3000	15284	3000	1000	2000	1000	2000	1	1000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2s, v1.2s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70205	120153	80120	40101	30018	10001	30130	30027	10014	3211537	1209821	3087076	70180	30240	10015	30045	60216	10003	30009	40001	10000	20000	40100
70204	120052	80107	40101	30006	10000	30103	30002	10003	3208687	1208798	3084337	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120042	80104	40101	30003	10000	30103	30002	10014	3209069	1208991	3084715	70181	30244	10015	30045	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120040	80104	40101	30003	10000	30103	30002	10003	3208736	1208877	3084394	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70026	120182	80040	40016	30022	10002	30070	30057	10003	3209177	1209506	3084723	70018	30028	10003	30009	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120075	80024	40016	30007	10001	30043	30032	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3208863	1209343	3084418	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120042	80014	40011	30003	10000	30010	30000	10000	3209025	1209409	3084574	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70025	120118	80024	40016	30007	10001	30043	30032	11140	3320508	1237218	3087478	73237	32789	11382	30060	60106	10015	30046	40006	10000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2s, v1.2s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70206	120205	80132	40108	30022	10002	30162	30057	10002	3208929	1208836	3084554	70107	30206	10003	30009	60358	10027	30080	40015	10000	20000	40100
70204	120049	80107	40101	30006	10000	30103	30002	10003	3208876	1208868	3084512	70108	30208	10003	30009	60290	10015	30044	40009	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70205	120095	80117	40106	30010	10001	30133	30032	10003	3208979	1208969	3084621	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70204	120047	80107	40101	30006	10000	30103	30002	10003	3208925	1208947	3084569	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100
70205	120080	80117	40106	30010	10001	30133	30032	10003	3209249	1209075	3084881	70108	30208	10003	30009	60216	10003	30009	40001	10000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
70025	120169	80030	40011	30018	10001	30040	30027	10003	3209032	1209391	3084574	70018	30028	10003	30009	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120054	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60104	10015	30043	40006	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209133	1209446	3084671	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010
70024	120049	80017	40011	30006	10000	30010	30000	10000	3209052	1209413	3084593	70010	30020	10000	30000	60020	10000	30000	40001	10000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240205	80154	240196	101	160074	80021	100	160036	80006	300	240035	973330	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240082	1600502	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240041	1600490	240114	200	80007	160013	200	80037	160071	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240070	1600502	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100
240204	80056	240125	101	160020	80004	100	160008	80006	300	240035	1600490	240114	200	80007	160013	200	80007	160013	1	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240025	80156	240101	11	160070	80020	10	160034	80006	30	240054	1116276	240024	20	80007	160013	20	80007	160013	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240038	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240018	1600470	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80057	240031	11	160020	80000	10	160000	80115	30	242903	1332686	240351	20	80115	160226	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80034	36	241552	1570322	240108	22	80035	160069	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10
240024	80056	240031	11	160020	80000	10	160000	80000	30	240017	1600444	240010	20	80000	160000	20	80000	160000	1	80000	160000	10

LD2 (multiple, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations