Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (multiple, 4H)

Test 1: uops

Code:

  ld2 { v0.4h, v1.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630062968430331203010022004100030001527030001000200010002000110002000
630042936630031200210002000100030001527030001000200010002000110002000
630042933630031200210002000100030001527030001000200010002000110002000
630042933830031200210002000100030001527030001000200010002000110002000
630042933530031200210002000100030001527030001000200010002000110002000
630042933630031200210002000100030001527030001000200010002000110002000
630042933630031200210002000100030021527430001000200010002000110002000
630042998230031200210002000100030001527030001000200010002000110002000
630043015630031200210002000100030001527030001000200010002000110002000
630042948930031200210002000100030001527030001000200010002000110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4h, v1.4h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120149801204010130018100013013030027100033208888120887630845247010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960286100153004640007100002000040100
70204120047801074010130006100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70205120073801144010630007100013013330032100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120111801044010130003100003010330002100023208993120896230846467010730206100033000960216100033000940001100002000040100
70204120041801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120047801074010130006100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100033000940001100002000040100
70205120136801144010630007100013013330032100033208925120894730845697010830208100033000960216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120149800304001130018100013004030027100033209069120946230846197001830028100033000960020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209133120944530846707001030020100003000060020100003000040001100002000040010
70025120103800274001630010100013004330032100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120055800174001130006100003001030000100003209106120943530846457001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060172100273008140010100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060020100003000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4h, v1.4h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120152801204010130018100013013030027100033208996120891630846247010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033209141120902730847727010830208100033000960216100033000940001100002000040100
70205120083801174010630010100013013330032100033209033120898730846717010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033209060120899730846977010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100153211052120976330866007018230244100153004360216100033000940001100002000040100
70205120083801174010630010100013013330034100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033209114120902230847497010830208100033000960216100033000940001100002000040100
70205120130801164010530009100023013330031100033209033120898730846717010830208100033000960288100153004540006100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70026120188800404001630022100023007030057100033209015120944230845697001830028100033000960036100033000940001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120048800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120050800174001130006100003001030000100003208998120939330845437001030020100003000060110100153004440006100002000040010
70025120080800274001630010100013004330032100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120051800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120050800174001130006100003001030000117973321390124553430882357487933952120743012160020100003000040001100002000040010
70024120048800174001130006100003001030000100003209079120942630846217001030020100003000060020100003000040001100002000040010
70024120079800174001130006100003001030000100003209106120943730846477001030020100003000060020100003000040001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
2402058017224019510116007480020100160034800063002400349668982401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024004416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024004516004382401142008000716001320080037160071180000160000100
240204800592401251011600208000410016000848724414541748119255401453175030489139296320080007160013180000160000100
24020480058240125101160020800041001600088000630024003516004642401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002680235240168111601148004310160082800063024003412164582400242080007160013208000016000018000016000010
24002480054240031111600208000010160000800003024003816003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800363024149715733822401102080037160071208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010
24002480054240031111600208000010160000800003024001616003922400102080000160000208000016000018000016000010