Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (multiple, 4S)

Test 1: uops

Code:

  ld2 { v0.4s, v1.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.004

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
640053056440331202820042004200060001529040002000200020004000120002000
640043011540051200420002000200060001529040002000200020004000120002000
640042969940051200420002000200060001529040002000200020004000120002000
640042969140051200420002000200060001529040002000200020004000120002000
640042968240051200420002000200060001529040002000200020004000120002000
640042969840051200420002000200060001529040002000200020004000120002000
640042966240051200420002000200060001529040002000200020004000120002000
640042969640051200420002000200060001529040002000200020004000120002000
640042966140051200420002000200060001529040002000200020004000120002000
640042970140051200420002000200060001529040002000200020004000120002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4s, v1.4s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
80205120149901214010130018200023013030024200043208941213913830845128010930209200063000960218200065001540001200002000040100
80204120049901074010130006200003010330002200043208908213911630844868010930209200063000960218200065001540001200002000040100
80204120049901074010130006200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80205120138901184010630010200023013330032200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120049901074010130006200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120049901074010130006200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120049901074010130006200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120058901074010130006200003010330002200043208952213918830845368010930209200063000960284200265006640006200002000040100
80204120049901074010130006200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120049901074010130006200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
80025120159900314001130018200023004030024200003209022213914030845078001030020200003000060020200005000040001200002000040010
80024120049900174001130006200003001030000200243209147213925430846388009930062200263004060020200005000040001200002000040010
80024120049900174001130006200003001030000200003208914213908230844318001030020200003000060020200005000040001200002000040010
80024120050900174001130006200003001330002200043208796213904030843368001930029200063000960038200065001540001200002000040010
80024120048900174001130006200003001330002200043208796213904030843368001930029200063000960038200065001540001200002000040010
80024120050900174001130006200003001330002200043208796213904030843368001930029200063000960038200065001540001200002000040010
80024120047900174001130006200003001330002200043208796213904030843368001930029200063000960038200065001540001200002000040010
80025120080900284001630010200023004330032200043209282213936430848048001930029200063000960020200005000040001200002000040010
80024120052900174001130006200003001030000200003208779213899630843098001030020200003000060020200005000040001200002000040010
80024120047900174001130006200003001030000200003208779213899630843098001030020200003000060020200005000040001200002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4s, v1.4s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
80205120497901214010130018200023013030024200043208832213898430843688010930209200063000960218200065001540001200002000040100
80204120052901074010130006200003010330002200243209435213948030849478018930242200263004060218200065001540001200002000040100
80204120042901044010130003200003010330002200043208870213905030844418010930209200063000960218200065001540001200002000040100
80204120042901044010130003200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120042901044010130003200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120042901044010130003200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80205120144901184010630010200023013330032200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120042901044010130003200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100
80204120042901044010130003200003010330002200043210761214039430862788010930209200063000960218200065001540001200002000040100
80204120042901044010130003200003010330002200043208952213918830845368010930209200063000960218200065001540001200002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
80025120147900314001130018200023004030024200043209001213911830844898001930029200063000960170200465011740011200002000040010
80024120071900204001130009200003001030000200003209022213914030845078001030020200003000060020200005000040001200002000040010
80024120049900174001130006200003001030000200003209022213914030845078001030020200003000060020200005000040001200002000040010
80024120049900174001130006200003001030000200003209022213914030845078001030020200003000060020200005000040001200002000040010
80024120049900174001130006200003001030000200003209022213914030845078001030020200003000060020200005000040001200002000040010
80024120049900174001130006200003001030000200003209022213914030845078001030020200003000060170200465011740011200002000040010
80024120074900204001130009200003001030000200003209022213914030845078001030020200003000060020200005000040001200002000040010
80024120050900174001130006200003001030000200003209022213914030845078001030020200003000060020200005000040001200002000040010
80024120049900174001130006200003001030000200003209049213915830845338001030020200003000060020200005000040001200002000040010
80024120054900174001130006200003001030000200043209012213916830845128001930029200063000960020200005000040001200002000040010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0019

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
3202058028332026710116012816003810016003816001230048021012802243201242001600121600122001600123200241160000160000100
3202058022632022710116008816003810016005416001230053233413321663201242001600121600122001600543201081160000160000100
3202048015432013510116002616000810016001216001230049176412917723201242001600121600122001600123200241160000160000100
3202048015032013510116002616000810016001216001230048021012802223201242001600121600122001600123200241160000160000100
3202048015032013510116002616000810016001216001230048020812802223201242001600121600122001600543201081160000160000100
3202048020432013510116002616000810016001216001230049628412962803201242001600121600122001600123200241160000160000100
3202048015032013510116002616000810016001216001230048522412852203201242001600121600122001600123200241160000160000100
3202048015032013510116002616000810016001216001230048021012802223201242001600121600122001600123200241160000160000100
3202048015032013510116002616000810016001216001230048263612826403201242001600121600122021600543201082160000160000100
3202048016232013510116002616000810016001216001230048951612895603201242001600121600122001600123200241160000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
3200258054432017711160128160038101600381600123048028412806423200342016001216001220160000320000116000016000010
3200248006432004711160036160000101600001600003048017412803263200102016000016000020160000320000116000016000010
3200248006932003111160020160000101600001600003051236013124963200102016000016000020160000320000116000016000010
3200248005632003111160020160000101600001600003048017212803263200102016000016000020160000320000116000016000010
3200248014632003111160020160000101600001600003065405614541443200102016000016000020160000320000116000016000010
3200248005632003111160020160000101600001600003048017412803263200102016000016000020160000320000116000016000010
3200248005632003111160020160000101600001600003048017212803263200102016000016000020160000320000116000016000010
3200248005632003111160020160000101600001600003048014012804083200102016000016000020160000320000116000016000010
3200248005632003111160020160000101600001600003048017412803263200102016000016000020160000320000116000016000010
3200248005632003111160020160000101600001600003049360212937543200102016000016000020160054320108116000016000010