Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (multiple, 8B)

Test 1: uops

Code:

  ld2 { v0.8b, v1.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630053013230311202810022004100030001528830001000200010002000110002000
630042937930051200410002000100030001527430001000200010002000110002000
630052960930031200210002000100030001527430001000200010002000110002000
630042950530031200210002000100030001527430001000200010002000110002000
630042936930031200210002000100030001527430001000200010002000110002000
630042938230031200210002000100030001527430001000200010002000110002000
630042951230031200210002000100030001527430001000200010002000110002000
630042998030031200210002000100030001529030001000200010012002110002000
630042936530031200210002000100030001527430001000200010002000110002000
630042936930031200210002000100030001527430001000200010002000110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8b, v1.8b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120155801204010130018100013013030027100033208893120881730845157010830208100033000960216100033000940001100002000040100
70204120051801074010130006100003010330002100033209087120900830847237010830208100033000960216100033000940001100002000040100
70205120082801174010630010100013013330032100023208801120884430844467010730206100033000960216100033000940001100002000040100
70204120050801074010130006100003010330002100033209087120900730847237010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100143209309120907830849277017930242100153004360216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70205120147801174010630010100013013330032100033208844120891930844967010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033209114120901930847497010830208100033000960216100033000940001100002000040100
70204120127801074010130006100003010330002100033209159120903830847927010830208100033000960216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120153800304001130018100013004030027100033209015120944230845697001830028100033000960020100003000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060104100153004340006100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120048800174001130006100003001030000100143209342120955030848757008930064100153004560020100003000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003208998120939330845437001030020100003000060020100003000040001100002000040010
70024120049800174001130006100003001030000100003209133120944830846737001030020100003000060020100003000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8b, v1.8b }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70206120195801334010630025100023016030057100033209735120908730853067010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100033000940001100002000040100
70204120049801074010130006100003010330002100153209272120899230848727018030244100153004360216100033000940001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120518800304001130018100013004030027100003208836120933330843937001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120104800144001130003100003001030000100003208863120934430844207001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100143209153120947130847017008930063100153004660020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100003000040001100002000040010
70024120040800144001130003100003001030000100003208890120935330844467001030020100003000060020100003000040001100002000040010
70025120132800304001630013100013004330032100033208843120932130843997001830028100033000960020100003000040001100002000040010
70024120047800144001130003100003001030000100003208772120925130843237001030020100003000060020100003000040001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.8b, v1.8b }, [x6]
  ld2 { v0.8b, v1.8b }, [x6]
  ld2 { v0.8b, v1.8b }, [x6]
  ld2 { v0.8b, v1.8b }, [x6]
  ld2 { v0.8b, v1.8b }, [x6]
  ld2 { v0.8b, v1.8b }, [x6]
  ld2 { v0.8b, v1.8b }, [x6]
  ld2 { v0.8b, v1.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
2402058016324019610116007480021100160036800063002400349860582401142008000716001320080007160013180000160000100
24020480046240117101160012800041001600088003730024013516008882402012008003716007120080007160013180000160000100
24020480046240117101160012800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088003430024118510735902401962008003516006920080007160013180000160000100
24020480046240117101160012800041001600088000630024008716002342401142008000716001320080007160013180000160000100
24020480046240117101160012800041001600088000630024003116002342401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003116002342401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480054240125101160020800041001600088000630024003416004382401142008000716001320080007160013180000160000100
24020480046240117101160012800041001600088000630024003416004382401142008000716001320080007160013180000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580189240101111600708002010160034800063024005511155302400242080007160013208003716007118000016000010
24002480056240031111600208000010160000800003024002716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024150816008202400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024004616004562400102080000160000208003716007118000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010
24002480056240031111600208000010160000800003024001716004442400102080000160000208000016000018000016000010