Icestorm: LD2 (multiple, 8H) measurements

Code:

  ld2 { v0.8h, v1.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.004

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	29690	4033	1	2028	2004	2004	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29504	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29489	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29472	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29474	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29476	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29530	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29473	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29476	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000
64004	29576	4005	1	2004	2000	2000	2000	6000	15290	4000	2000	2000	2000	4000	1	2000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8h, v1.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120155	90121	40101	30018	20002	30130	30024	20004	3208854	2139084	3084442	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120051	90107	40101	30006	20000	30103	30002	20004	3208952	2139192	3084544	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80205	120080	90118	40106	30010	20002	30133	30032	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20024	3210329	2140096	3085838	80189	30242	20026	30040	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3209006	2139228	3084596	80109	30209	20006	30009	60284	20026	50066	40006	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120147	90031	40011	30018	20002	30040	30024	20000	3209011	2139096	3084496	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208833	2139032	3084361	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60104	20026	50066	40006	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208779	2138996	3084309	80010	30020	20000	30000	60086	20020	50051	40006	20000	20000	40010
80024	120040	90014	40011	30003	20000	30010	30000	20000	3208860	2139050	3084387	80010	30020	20000	30000	60104	20026	50066	40006	20000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8h, v1.8h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120147	90121	40101	30018	20002	30130	30024	20004	3208822	2139024	3084401	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120162	90107	40101	30006	20000	30103	30002	20004	3209033	2139246	3084622	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60280	20026	50065	40007	20000	20000	40100
80204	120050	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80205	120080	90118	40106	30010	20002	30133	30032	20004	3208908	2139120	3084494	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20024	3210896	2140472	3086390	80189	30242	20026	30040	60218	20006	50015	40001	20000	20000	40100
80204	120050	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120047	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100
80204	120127	90107	40101	30006	20000	30103	30002	20004	3208898	2139156	3084492	80109	30209	20006	30009	60218	20006	50015	40001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120151	90031	40011	30018	20002	30040	30024	20024	3209407	2139370	3084838	80099	30062	20026	30040	60038	20006	50015	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20024	3209282	2139334	3084750	80099	30062	20026	30040	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20024	3209254	2139316	3084730	80099	30062	20026	30040	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120050	90017	40011	30006	20000	30010	30000	20000	3209076	2139180	3084567	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010
80024	120047	90017	40011	30006	20000	30010	30000	20000	3208968	2139108	3084463	80010	30020	20000	30000	60020	20000	50000	40001	20000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0020

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	80280	320267	101	160128	160038	100	160038	160012	300	480272	1282096	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480272	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480272	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	498370	1300194	320124	200	160012	160012	15016	126059	232928	3761	121216	116410	3095
320204	80170	320153	101	160044	160008	100	160012	160096	300	513988	1316536	320292	200	160096	160096	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160180	320360	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480272	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100
320204	80160	320153	101	160044	160008	100	160012	160012	300	480268	1282092	320124	200	160012	160012	200	160012	320024	1	160000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	80195	320177	11	160128	160038	10	160038	160000	30	503036	1318428	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160000	30	480232	1296596	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160000	30	480232	1296596	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160054	30	480580	1297176	320118	20	160054	160054	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160000	30	480232	1296596	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160000	30	480232	1296596	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160000	30	480232	1296596	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160000	30	480232	1296596	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160000	30	480232	1296596	320010	20	160000	160000	20	160000	320000	1	160000	160000	10
320024	80066	320049	11	160038	160000	10	160000	160000	30	480236	1296596	320010	20	160000	160000	20	160000	320000	1	160000	160000	10

LD2 (multiple, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations