Icestorm: LD2 (multiple, post-index, 16B) measurements

Code:

  ld2 { v0.16b, v1.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.002

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	29766	5035	1003	2028	2004	1002	2004	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29512	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29522	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29526	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29553	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29512	5003	1001	2002	2000	1000	2000	2000	3000	6000	15285	5000	2000	2000	3000	4000	1001	2000	2000
64005	30176	5010	1002	2006	2002	1001	2002	2000	3000	6000	15272	5000	2000	2000	3000	4000	1001	2000	2000
64004	29773	5005	1001	2004	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29480	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29468	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.16b, v1.16b }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120147	100122	50102	30018	20002	40132	30030	20006	3199261	1898730	2903659	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120042	100104	50101	30003	20000	40104	30008	20006	3199127	1898764	2903698	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120042	100104	50101	30003	20000	40104	30008	20006	3199127	1898764	2903698	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120042	100104	50101	30003	20000	40104	30008	20006	3199127	1898764	2903698	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80205	120134	100119	50107	30010	20002	40135	30035	20006	3199127	1898764	2903698	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120042	100104	50101	30003	20000	40104	30008	20006	3199127	1898764	2903698	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120042	100104	50101	30003	20000	40104	30008	20006	3199127	1898764	2903698	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120042	100104	50101	30003	20000	40104	30008	20006	3199127	1898764	2903698	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120042	100104	50101	30003	20000	40104	30008	20006	3199127	1898764	2903698	90118	30209	20006	30009	60272	30036	50060	50007	20000	20000	40100
80204	120042	100104	50101	30003	20000	40104	30008	20006	3199127	1898764	2903698	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120151	100032	50012	30018	20002	40042	30030	20000	3199056	1899122	2904326	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120040	100014	50011	30003	20000	40010	30000	20000	3199137	1899170	2904393	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120040	100014	50011	30003	20000	40010	30000	20000	3199137	1899170	2904393	90010	30020	20000	30000	60038	30009	50015	50001	20000	20000	40010
80024	120049	100017	50011	30006	20000	40014	30008	20000	3199191	1899202	2904437	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120042	100014	50011	30003	20000	40010	30000	20000	3199191	1899202	2904437	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120042	100014	50011	30003	20000	40010	30000	20000	3199191	1899202	2904437	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120042	100014	50011	30003	20000	40010	30000	20000	3199191	1899202	2904437	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80025	120075	100026	50017	30007	20002	40045	30035	20000	3199137	1899056	2904252	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120042	100014	50011	30003	20000	40010	30000	20000	3199191	1899202	2904437	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120042	100014	50011	30003	20000	40010	30000	20000	3199191	1899202	2904437	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.16b, v1.16b }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0066

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120173	100122	50102	30018	20002	40132	30030	20024	3200017	1898924	2903987	90194	30236	20024	30036	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20024	3202103	1900620	2906344	90194	30239	20024	30037	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0044

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120155	100032	50012	30018	20002	40042	30030	20006	3199428	1899312	2904604	90028	30029	20006	30009	60020	30000	50000	50001	20000	20000	40010
80024	120044	100014	50011	30003	20000	40010	30000	20000	3199245	1899234	2904481	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120044	100014	50011	30003	20000	40010	30000	20000	3199245	1899234	2904481	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80025	120084	100029	50017	30010	20002	40045	30035	20000	3199245	1899234	2904481	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120044	100014	50011	30003	20000	40010	30000	20000	3199245	1899234	2904481	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120044	100014	50011	30003	20000	40010	30000	20000	3199245	1899234	2904481	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120044	100014	50011	30003	20000	40010	30000	20000	3199245	1899234	2904481	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120044	100014	50011	30003	20000	40010	30000	20000	3199245	1899234	2904481	90010	30020	20000	30000	60092	30036	50060	50007	20000	20000	40010
80024	120068	100014	50011	30003	20000	40010	30000	20000	3199245	1899234	2904481	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120044	100014	50011	30003	20000	40010	30000	20000	3199245	1899234	2904481	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.16b, v1.16b }, [x6], x8
  ld2 { v0.16b, v1.16b }, [x6], x8
  ld2 { v0.16b, v1.16b }, [x6], x8
  ld2 { v0.16b, v1.16b }, [x6], x8
  ld2 { v0.16b, v1.16b }, [x6], x8
  ld2 { v0.16b, v1.16b }, [x6], x8
  ld2 { v0.16b, v1.16b }, [x6], x8
  ld2 { v0.16b, v1.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2512

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	100219	400287	80121	160128	160038	80122	160038	160012	240318	480284	1280564	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160052	240378	480570	1281138	400230	200	160052	160052	200	240015	320020	80004	160000	160000	100
320205	100157	400247	80125	160084	160038	80126	160052	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	488604	1288850	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2506

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	100162	400197	80031	160128	160038	80032	160038	160010	240045	480278	1280728	400035	20	160010	160010	20	240000	320000	80001	160000	160000	10
320024	100056	400035	80011	160024	160000	80010	160000	160000	240030	482016	1282278	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320025	100105	400145	80035	160072	160038	80036	160052	160000	240030	480440	1280710	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100045	400035	80011	160024	160000	80010	160000	160000	240030	480148	1280418	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100045	400035	80011	160024	160000	80010	160000	160000	240030	480148	1280418	400010	20	160000	160000	20	240078	320104	80025	160000	160000	10
320024	100046	400035	80011	160024	160000	80010	160000	160000	240030	480148	1280418	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100046	400035	80011	160024	160000	80010	160000	160000	240030	480148	1280418	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100046	400035	80011	160024	160000	80010	160000	160000	240030	480148	1280418	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100046	400035	80011	160024	160000	80010	160000	160000	240030	480148	1280418	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100048	400035	80011	160024	160000	80010	160000	160000	240030	480148	1280418	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10

LD2 (multiple, post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations