Icestorm: LD2 (multiple, post-index, 2D) measurements

Code:

  ld2 { v0.2d, v1.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.002

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	30068	5035	1003	2028	2004	1002	2004	2000	3000	6000	15285	5000	2000	2000	3000	4000	1001	2000	2000
64004	29488	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29487	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29458	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29459	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29461	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29485	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29513	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29491	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000
64004	29506	5003	1001	2002	2000	1000	2000	2000	3000	6000	15270	5000	2000	2000	3000	4000	1001	2000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2d, v1.2d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120163	100122	50102	30018	20002	40132	30030	20006	3199120	1898430	2903295	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60272	30036	50060	50007	20000	20000	40100
80204	120058	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80205	120080	100119	50107	30010	20002	40135	30035	20006	3199478	1898988	2904016	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60272	30036	50060	50007	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120154	100032	50012	30018	20002	40042	30030	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60092	30036	50060	50007	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60092	30036	50060	50007	20000	20000	40010
80024	120112	100017	50011	30006	20000	40010	30000	20072	3205768	1903278	2910549	90326	30128	20072	30108	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2d, v1.2d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0068

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120187	100122	50102	30018	20002	40132	30030	20006	3199780	1899042	2904086	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20006	3199829	1899180	2904270	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20006	3199829	1899180	2904270	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20006	3199829	1899180	2904270	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20022	3200213	1899336	2904511	90190	30238	20024	30036	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20006	3199829	1899180	2904270	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20006	3199829	1899180	2904270	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20006	3199829	1899180	2904270	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20006	3199829	1899180	2904270	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120068	100104	50101	30003	20000	40104	30008	20024	3200267	1899402	2904596	90194	30236	20024	30036	60218	30009	50015	50001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120155	100032	50012	30018	20002	40042	30030	20006	3199383	1899288	2904570	90028	30029	20006	30009	60020	30000	50000	50001	20000	20000	40010
80024	120051	100017	50011	30006	20000	40010	30000	20000	3199434	1899346	2904635	90010	30020	20000	30000	60092	30036	50060	50007	20000	20000	40010
80024	120074	100020	50011	30009	20000	40014	30008	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20024	3199821	1899628	2905038	90104	30056	20024	30036	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.2d, v1.2d }, [x6], x8
  ld2 { v0.2d, v1.2d }, [x6], x8
  ld2 { v0.2d, v1.2d }, [x6], x8
  ld2 { v0.2d, v1.2d }, [x6], x8
  ld2 { v0.2d, v1.2d }, [x6], x8
  ld2 { v0.2d, v1.2d }, [x6], x8
  ld2 { v0.2d, v1.2d }, [x6], x8
  ld2 { v0.2d, v1.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2512

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	100201	400287	80121	160128	160038	80122	160038	160012	240318	480292	1280474	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100104	400139	80105	160026	160008	80106	160012	160012	240318	480218	1280230	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100098	400139	80105	160026	160008	80106	160012	160012	240318	480216	1280230	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100098	400139	80105	160026	160008	80106	160012	160012	240318	480216	1280230	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100098	400139	80105	160026	160008	80106	160012	160050	240375	480444	1280600	400225	200	160050	160050	200	240018	320024	80005	160000	160000	100
320204	100098	400139	80105	160026	160008	80106	160012	160012	240318	480218	1280230	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100098	400139	80105	160026	160008	80106	160012	160012	240318	480218	1280230	400130	200	160012	160012	200	240015	320020	80004	160000	160000	100
320204	100098	400139	80105	160026	160008	80106	160012	160012	240318	480218	1280230	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100098	400139	80105	160026	160008	80106	160012	160012	240318	480216	1280230	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100098	400139	80105	160026	160008	80106	160012	160012	240318	480218	1280230	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2507

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	100306	400197	80031	160128	160038	80032	160038	160012	240048	480312	1280796	400040	20	160012	160012	20	240000	320000	80001	160000	160000	10
320024	100063	400067	80015	160044	160008	80016	160012	160000	240030	480248	1280666	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100055	400049	80011	160038	160000	80010	160000	160000	240030	480248	1280664	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100054	400049	80011	160038	160000	80010	160000	160000	240030	480248	1280664	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100054	400049	80011	160038	160000	80010	160000	160000	240030	480242	1280664	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100054	400049	80011	160038	160000	80010	160000	160000	240030	489816	1290376	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100059	400049	80011	160038	160000	80010	160000	160000	240030	480248	1280664	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100053	400049	80011	160038	160000	80010	160000	160000	240030	480248	1280664	400010	20	160000	160000	20	240078	320104	80025	160000	160000	10
320024	100054	400049	80011	160038	160000	80010	160000	160000	240030	480248	1280664	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100054	400049	80011	160038	160000	80010	160000	160000	240030	480242	1280664	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10

LD2 (multiple, post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations