Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (multiple, post-index, 2S)

Test 1: uops

Code:

  ld2 { v0.2s, v1.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005295444033100320281002100220041000300030001529040001000200020002000100110002000
63004295384003100120021000100020001000300030001527440001000200020002000100110002000
63004293624003100120021000100020001000300030001527440001000200020002000100110002000
63004293334003100120021000100020001000300030001527440001000200020002000100110002000
63004293214003100120021000100020001000300030001527440001000200020002000100110002000
63004293434003100120021000100020001000300030001527440001000200020002000100110002000
63004293304003100120021000100020001000300030001527440001000200020002000100110002000
63004293604003100120021000100020001000300030001527440001000200020002000100110002000
63004293214003100120021000100020001000300030001527440001000200020002000100110002000
63004293314003100120021000100020001000300030001527440001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2s, v1.2s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015490121501023001810001401323003210003319923294936429065308011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020512008090118501073001010001401353003510003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412005290107501013000610000401043000810003319928294937729065908011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015490031500123001810001400423003210003319931594963029093418002330028100033000960036200063000950001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010012319960294976129096958009230059100123003760020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002512007690025500173000710001400453003510003319937694970429094668002530029100043000960020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010000319916194959729091078001030020100003000060020200003000050001100002000040010
7002412004090014500113000310000400103000010012319959894975829096258009230059100123003760020200003000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2s, v1.2s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2442

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020612257190134501103002210002401653005810003326431496865529588548011430208100033000960216200063000950001100002000040100
7020412244990107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244790107501013000610000401043000710003326390796857729586038011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960276200243003750007100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2917

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512313090031500123001810001400423003110003327949797333029731858002330028100033000960020200003000050001100002000040010
7002412291790017500113000610000400103000010012327888597324429727808009230059100123003760020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002512297890028500173001010001400453003510000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010
7002412291790017500113000610000400103000010000327682897260729708498001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0013

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580355320251801221601088002180123160036800063574513571111266319320122200800061600122001600141600138000680000160000100
24020480103320143801051600348000480106160010800073377453374201270095320124200800071600132001600121600128000580000160000100
24020480104320147801061600368000580108160012800073352993349671272340320123200800071600132001600701600698003480000160000100
24020480104320147801061600368000580108160012800073416763413451276323320124200800071600132001600141600138000680000160000100
24020480104320146801061600358000580107160010800073324283321071268331320124200800071600132001600141600138000580000160000100
24020480119320147801061600368000580107160010800073350823350491318634320124200800071600132001600181600178000780000160000100
24020480110320151801071600388000680108160012800073416763413451276323320124200800071600132001600761600748003680000160000100
24020480110320144801051600358000480107160010800073380843377651275371320124200800071600132001600161600168000680000160000100
24020480104320144801051600358000480107160010800073363503360231280103320125200800081600162001600141600138000580000160000100
24020480103320139801041600328000380106160008800073328523325241273934320124200800071600132001600141600138000580000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002580189320153800301601048001980032160034800003800583800281376392320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003211383211131598364320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003217423217171600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003256863256611600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003199853199601600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003198513198261600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003356853356581600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003217423217171600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003273323273061600192320010208000016000020160000160000800018000016000010
24002480046320031800111600208000080010160000800003217423217171600192320010208000016000020160000160000800018000016000010