Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (multiple, post-index, 4H)

Test 1: uops

Code:

  ld2 { v0.4h, v1.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005298224069100720561006100620121000300030001528440001000200020002000100110002000
63004293984003100120021000100020001000300030001527040001000200020002000100110002000
63004294054003100120021000100020001000300030001527040001000200020002000100110002000
63004294104003100120021000100020001000300030001527040001000200020002000100110002000
63004293974003100120021000100020001000300030001527040001000200020002000100110002000
63004294104003100120021000100020001000300030001527040001000200020002000100110002000
63004293944003100120021000100020001000300030001527040001000200020002000100110002000
63004294064003100120021000100020001000300030001527040001000200020002000100110002000
63004294084003100120021000100020001000300030001527040001000200020002000100110002000
63005294234003100120021000100120021000300030001527040001000200020002000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4h, v1.4h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015090121501023001810001401323003210003319922994930729064218011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200063000950001100002000040100
7020412004990107501013000610000401043000710003319947594949529068738011430208100033000960218200083000950001100002000040100
7020412004790107501013000610000401043000710003319923394936429065478011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020512008090120501093001010001401373003310003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100
7020412004790107501013000610000401043000710003319928694943429066928011430208100033000960216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015990031500123001810001400423003210000319930494958729091308001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010012319975794980329096758009230058100133003760020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200003000050001100002000040010
7002412005090017500113000610000400103000010000319940494967129093328001030020100003000060020200003000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4h, v1.4h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2442

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020612256290132501083002210002401633006010003326398596848829584318011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326371896852129584288011430208100033000960278200243003750007100002000040100
7020412244290107501013000610000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710003326371896852129584288011430208100033000960216200063000950001100002000040100
7020412244290107501013000610000401043000710012326379096852729584398018230239100123003760216200063000950001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2908

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512301990031500123001810001400423003210003327952097339229733188002330028100033000960036200063000950001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060096200263003750006100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327663997255329706768001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010003327838197311329723948002530029100043000960036200063000950001100002000040010
7002412291590017500113000610000400103000010000328012297370729739938001030020100003000060020200003000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200003000050001100002000040010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020580226320250801221601078002180123160036800063555243551851259162320122200800061600122001600161600168000680000160000100
24020480109320135801061600248000580106160010800073366313364681292353320124200800071600132001600161600168000680000160000100
24020480095320135801051600268000480107160010800073307203304001274821320124200800071600132001600121600108000480000160000100
24020480095320134801051600258000480107160010800083364063360711279854320128200800081600162001600161600168000680000160000100
24020480095320134801051600258000480107160010800073368393365001287645320124200800071600132001600141600138000580000160000100
24020480095320137801061600268000580108160012800353523523520161293110320237200800351600692001600141600138000680000160000100
24020480095320136801061600258000580107160010800073344383341191285083320124200800071600132001600141600138000680000160000100
24020480095320132801051600238000480107160009800063334233331021282683320120200800061600102001600141600138000680000160000100
24020480098320134801051600258000480107160010800083364063360801279854320128200800081600162001600141600138000680000160000100
24020480095320134801051600258000480107160010800073298993295781260234320124200800071600132001601341601338006480000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002680253320293800611601828005080063160093800073217693217451563162320035208000816001620160012160010800048000016000010
24002480055320035800111600248000080010160000800003225043224771556285320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003379983379721570471320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800083380333380071570551320038208000816001620160000160000800018000016000010
24002480048320035800111600248000080010160000800003338833338591562891320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003213953213711558441320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003213953213711558441320010208000016000020160000160000800018000016000010
24002580106320161800441600848003380046160068800003290843290611568315320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003221663221431569361320010208000016000020160000160000800018000016000010
24002480048320035800111600248000080010160000800003221663221431569361320010208000016000020160000160000800018000016000010