Icestorm: LD2 (multiple, post-index, 4S) measurements

Code:

  ld2 { v0.4s, v1.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.002

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	29616	5035	1003	2028	2004	1002	2004	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29423	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29415	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29408	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29409	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29423	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29423	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29406	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29409	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29423	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4s, v1.4s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120153	100122	50102	30018	20002	40132	30030	20006	3198925	1898310	2903093	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80205	120073	100118	50109	30007	20002	40137	30033	20006	3199073	1898732	2903654	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120040	100104	50101	30003	20000	40104	30008	20006	3199073	1898732	2903654	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120040	100104	50101	30003	20000	40104	30008	20006	3199073	1898732	2903654	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120040	100104	50101	30003	20000	40104	30008	20006	3199073	1898732	2903654	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120040	100104	50101	30003	20000	40104	30008	20006	3199073	1898732	2903654	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120040	100104	50101	30003	20000	40104	30008	20006	3199073	1898732	2903654	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120040	100104	50101	30003	20000	40104	30008	20006	3199073	1898732	2903654	90118	30209	20006	30009	60272	30036	50060	50007	20000	20000	40100
80204	120040	100104	50101	30003	20000	40104	30008	20006	3199073	1898732	2903654	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120040	100104	50101	30003	20000	40104	30008	20006	3199073	1898732	2903654	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120149	100032	50012	30018	20002	40042	30030	20006	3199302	1899240	2904504	90028	30029	20006	30009	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80025	120080	100029	50017	30010	20002	40045	30035	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60092	30036	50060	50007	20000	20000	40010
80024	120062	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120047	100017	50011	30006	20000	40010	30000	20000	3199326	1899282	2904547	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4s, v1.4s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0075

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120179	100122	50102	30018	20002	40132	30030	20006	3199895	1899000	2904044	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120075	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120075	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120075	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120081	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60274	30036	50056	50007	20000	20000	40100
80204	120075	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120075	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120075	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120075	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120075	100107	50101	30006	20000	40104	30008	20006	3200018	1899292	2904424	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80026	120184	100044	50018	30022	20004	40073	30057	20006	3199409	1899304	2904592	90028	30029	20006	30009	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80025	120084	100029	50017	30010	20002	40045	30035	20000	3200055	1899714	2905141	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120053	100017	50011	30006	20000	40010	30000	20000	3199488	1899378	2904679	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2512

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	100219	400287	80121	160128	160038	80122	160038	160052	240378	486780	1287276	400230	200	160052	160052	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100099	400140	80104	160030	160006	80105	160010	160012	240318	480184	1280314	400130	200	160012	160012	200	240015	320020	80004	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100100	400143	80105	160030	160008	80106	160012	160010	240315	480178	1280302	400125	200	160010	160010	200	240018	320024	80005	160000	160000	100
320204	100099	400140	80104	160030	160006	80105	160010	160050	240375	480602	1280914	400225	200	160050	160050	200	240018	320024	80005	160000	160000	100
320204	100099	400140	80104	160030	160006	80105	160010	160012	240318	480184	1280314	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2507

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	100169	400197	80031	160128	160038	80032	160038	160012	240048	480292	1280652	400040	20	160012	160012	20	240000	320000	80001	160000	160000	10
320024	100058	400047	80011	160036	160000	80010	160000	160000	240030	481596	1281750	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100052	400047	80011	160036	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100051	400047	80011	160036	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240078	320104	80025	160000	160000	10
320024	100051	400047	80011	160036	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100052	400047	80011	160036	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100051	400047	80011	160036	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100051	400047	80011	160036	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100052	400047	80011	160036	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100053	400047	80011	160036	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240078	320104	80025	160000	160000	10

LD2 (multiple, post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations