Icestorm: LD2 (multiple, post-index, 8H) measurements

Code:

  ld2 { v0.8h, v1.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.002

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64005	29606	5035	1003	2028	2004	1002	2004	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29462	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29450	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29437	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29455	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29426	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29467	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29461	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29459	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000
64004	29461	5003	1001	2002	2000	1000	2000	2000	3000	6000	15274	5000	2000	2000	3000	4000	1001	2000	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8h, v1.8h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120151	100122	50102	30018	20002	40132	30030	20006	3199166	1898568	2903450	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80205	120090	100124	50109	30013	20002	40137	30033	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80205	120140	100125	50107	30016	20002	40135	30035	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120047	100107	50101	30006	20000	40104	30008	20006	3199262	1898844	2903808	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120147	100032	50012	30018	20002	40042	30030	20000	3199380	1899314	2904591	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120049	100017	50011	30006	20000	40010	30000	20024	3200843	1900272	2905950	90104	30056	20024	30036	60020	30000	50000	50001	20000	20000	40010
80024	120057	100017	50011	30006	20000	40010	30000	20000	3199380	1899314	2904591	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120049	100017	50011	30006	20000	40010	30000	20000	3199380	1899314	2904591	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120049	100017	50011	30006	20000	40010	30000	20000	3199461	1899368	2904669	90010	30020	20000	30000	60092	30036	50060	50007	20000	20000	40010
80024	120158	100037	50021	30012	20004	40044	30027	20000	3199407	1899330	2904613	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120049	100017	50011	30006	20000	40010	30000	20018	3200977	1900304	2906078	90089	30047	20018	30027	60020	30000	50000	50001	20000	20000	40010
80024	120050	100017	50011	30006	20000	40010	30000	20000	3201972	1901042	2907086	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120147	100037	50021	30012	20004	40044	30027	20018	3201054	1900358	2906157	90089	30047	20018	30027	60146	30063	50105	50017	20000	20000	40010
80024	120151	100037	50021	30012	20004	40044	30027	20018	3201112	1900394	2906208	90089	30047	20018	30027	60020	30000	50000	50001	20000	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8h, v1.8h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0066

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	120251	100122	50102	30018	20002	40132	30030	20024	3201293	1900054	2905512	90194	30236	20024	30036	60218	30009	50015	50001	20000	20000	40100
80204	120073	100107	50101	30006	20000	40104	30008	20006	3199936	1899130	2904209	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120073	100107	50101	30006	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120073	100107	50101	30006	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80205	120101	100118	50109	30007	20002	40137	30033	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199964	1899260	2904380	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199775	1899148	2904226	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100
80204	120066	100104	50101	30003	20000	40104	30008	20006	3199964	1899260	2904380	90118	30209	20006	30009	60218	30009	50015	50001	20000	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	120156	100032	50012	30018	20002	40042	30030	20006	3199483	1899458	2904788	90028	30029	20006	30009	60020	30000	50000	50001	20000	20000	40010
80024	120051	100017	50011	30006	20000	40010	30000	20000	3199434	1899346	2904635	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120051	100017	50011	30006	20000	40010	30000	20000	3199434	1899346	2904635	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80025	120084	100029	50017	30010	20002	40045	30035	20000	3199757	1899452	2904815	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120051	100017	50011	30006	20000	40010	30000	20000	3199434	1899346	2904635	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120051	100017	50011	30006	20000	40010	30000	20000	3199434	1899346	2904635	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120051	100017	50011	30006	20000	40010	30000	20000	3199434	1901846	2904635	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120051	100017	50011	30006	20000	40010	30000	20000	3199515	1899400	2904713	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80025	120081	100029	50017	30010	20002	40045	30035	20000	3199434	1899346	2904635	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010
80024	120051	100017	50011	30006	20000	40010	30000	20000	3199434	1899346	2904635	90010	30020	20000	30000	60020	30000	50000	50001	20000	20000	40010

Test 4: throughput

Count: 8

Code:

  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2513

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	100974	400527	80181	160218	160128	80182	160158	160052	240378	486100	1288282	400230	200	160052	160052	200	240018	320024	80005	160000	160000	100
320204	101022	400634	80224	160224	160186	80225	160250	160372	240858	491300	1294992	401030	200	160372	160372	200	240195	320260	80065	160000	160000	100
320204	100108	400157	80105	160044	160008	80106	160012	160012	240318	480284	1280560	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100108	400157	80105	160044	160008	80106	160012	160012	240318	480284	1280560	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100108	400157	80105	160044	160008	80106	160012	160012	240318	480278	1280560	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100108	400157	80105	160044	160008	80106	160012	160052	240378	480516	1280942	400230	200	160052	160052	200	240018	320024	80005	160000	160000	100
320204	100108	400157	80105	160044	160008	80106	160012	160012	240318	480278	1280560	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100108	400157	80105	160044	160008	80106	160012	160012	240318	480278	1280560	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100108	400157	80105	160044	160008	80106	160012	160012	240318	480284	1280560	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100
320204	100108	400157	80105	160044	160008	80106	160012	160012	240318	480284	1280560	400130	200	160012	160012	200	240018	320024	80005	160000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2506

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	100177	400197	80031	160128	160038	80032	160038	160000	240030	480256	1280576	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100044	400031	80011	160020	160000	80010	160000	160000	240030	480182	1280334	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100044	400031	80011	160020	160000	80010	160000	160000	240030	480180	1280334	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100053	400047	80011	160036	160000	80010	160000	160000	240030	480182	1280334	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100045	400031	80011	160020	160000	80010	160000	160000	240030	480182	1280334	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320025	100097	400129	80035	160056	160038	80036	160052	160000	240030	487464	1287588	400010	20	160000	160000	20	240240	320320	80081	160000	160000	10
320024	100045	400033	80011	160022	160000	80010	160000	160000	240030	480642	1280794	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100045	400031	80011	160020	160000	80010	160000	160000	240030	480182	1280334	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100044	400031	80011	160020	160000	80010	160000	160000	240030	480256	1280574	400010	20	160000	160000	20	240000	320000	80001	160000	160000	10
320024	100400	400271	80071	160110	160090	80070	160120	160280	240450	491314	1294878	400710	20	160280	160280	20	240300	320400	80101	160000	160000	10

LD2 (multiple, post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations