Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (single, B)

Test 1: uops

Code:

  ld2 { v0.b, v1.b }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630062976430191201610022004100030001528430001000200010004000110002000
630052937830051200410002000100030001528430001000200010004000110002000
630042938830051200410002000100030001528430001000200010004000110002000
630042935330051200410002000100030001528430001000200010004000110002000
630042934930051200410002000100030001528430001000200010004000110002000
630042935130051200410002000100030001528430001000200010004000110002000
630042935330051200410002000100030001528430001000200010004000110002000
630042935230051200410002000100030001528430001000200010004000110002000
630042935330051200410002000100030001528430001000200010004000110002000
630042934930051200410002000100030001528430001000200010004000110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.b, v1.b }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120304801204010130018100013013030027100033209016120886830846297010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120053801044010130003100003010330002100143209343120909630849747018030244100153004660284100155007140006100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960284100155007140006100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100133209111120901130847397018030244100153004560284100155007140006100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025122365800304001130018100013004030027100033208978120937130845247001830028100033000960020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70026120155800374002130014100023007330062100003209133120944830846737001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003209133120944830846737001030020100003000060020100005000040001100002000040010
70025120073800244001630007100013004330032100003209360120947630848837001030020100003000060036100035001540001100002000040010
70024120042800144001130003100003001030000100003208863120934330844187001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000100003208863120934330844187001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000100003208863120934330844187001030020100003000060020100005000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.b, v1.b }[1], [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120156801204010130018100013013030027100033208753120882630843997010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208817120890730844697010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960286100155007640006100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100133210084120938630856847017830242100153004663118125595012541485112982003242287
70204120042801044010130003100003010330002100023208781120887630844407010730206100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70024120101800174001130006100003001330002100003208961120932230844967001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060104100155007140006100002000040010
70024120052800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120128800174001130006100003001030000100003209457120957830849857001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100143209342120955130848757008930062100153004360020100005000040001100002000040010
70024120047800174001130006100003001030000100133209793120971630852957008830062100153004660020100005000040001100002000040010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2512

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205100499240220101160100800191001600358000530024002312207252401142008000516000920080005320020180000320000100
400204100109240138101160034800031001600098000530024002212205402401152008000516001020080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024004312206042401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024002512205542401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2641

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400026103398240186111601368003910160075800053024002312210492400242080005160009208000532001818000032000010
400024101620240041111600308000010160000800003024000812208462400102080000160000208000032000018000032000010
400025101455240100111600688002110160042800003024001212208342400102080000160000208000032000018000032000010
400024101127240041111600308000010160000800003024003412209302400102080000160000208000032000018000032000010
400024101144240041111600308000010160000800003024000812208022400102080000160000208000032000018000032000010
400024101334240041111600308000010160000800253024008312212052400842080025160049208000032000018000032000010
400024101086240041111600308000010160000800003024000812208332400102080000160000208000032000018000032000010
400024101134240041111600308000010160000800003024000812208222400102080000160000208000032000018000032000010
400024101117240041111600308000010160000800003024000812208332400102080000160000208000032000018000032000010
400024101087240041111600308000010160000800003024000812208242400102080000160000208000032000018000032000010