Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (single, D)

Test 1: uops

Code:

  ld2 { v0.d, v1.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6300530095301712014100202004100030001528430001000200010004000110002000
6300429997300512004100002000100030001528830001000200010004000110002000
6300429684300512004100002000100030001528430001000200010004000110002000
6300429361300512004100002000100030001528430001000200010004000110002000
6300429373300512004100002000100030001528430001000200010004000110002000
6300429365300512004100002000100030001528430001000200010004000110002000
6300429611300512004100002000100030001528430001000200010004000110002000
6300429511300512004100002000100030001528430001000200010004000110002000
6300429361300512004100002000100030001528430001000200010004000110002000
6300429371300512004100002000100030001528430001000200010004000110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.d, v1.d }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120161801204010130018100013013030027100143209229120893230848317017930242100153004360216100035001540001100002000040100
70204120049801074010130006100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70205120075801144010630007100013013330034100033209033120899530846787010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120044801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120048801044010130003100003010330002100033208871120892730845227010830208100033000960216100035001540001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70026120330800404001630022100023007030057100033209177120950430847257001830028100033000960020100005000040001100002000040010
70024120047800174001130006100003001030000100003208809120932330843687001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060108100155007140006100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208863120934530844207001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060104100155007340006100002000040010
70024120043800144001130003100003001030000100003208809120932330843687001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000102073219854121384130860347057930508102373004460032100035001540001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.d, v1.d }[1], [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120516801204010130018100013013030027100033208893120881730845177010830208100033000960216100035001540001100002000040100
70205120135801204010630013100013013330032100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120051801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120056801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70205120089801204010630013100013013330032100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120053801074010130006100003010330002100033209060120900030846977010830208100033000960216100035001540001100002000040100
70204120051801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120521800304001130018100013004030027100033209015120944230845697001830028100033000960108100155007340006100002000040010
70024120040800144001130003100003001330002100033209015120944230845697001830028100033000960020100005000040001100002000040010
70024120040800144001130003100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100143209531120962130850507008930062100153004360020100005000040001100002000040010
70024120040800144001130003100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003209160120945330846937001030020100003000060020100005000040001100002000040010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2512

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205100483240220101160100800191001600358000530024002312207302401142008000516000920080005320020180000320000100
400204100104240140101160035800041001600108002530024008912211052401752008002516005020080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098002730024008812208492401792008002716005220080005320018180000320000100
400205100134240190101160063800261001600528000530024003512208162401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024003412205802401142008000516000920080005320018180000320000100
400204100112240140101160035800041001600108000530024009412208262401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100
400204100096240124101160020800031001600098000530024002212205322401142008000516000920080005320018180000320000100
400205100132240183101160058800241001600508000530024002312207302401142008000516000920080005320018180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2639

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025102832240132111601018002010160036800263024008612214032400872080026160051208000032000018000032000010
400025102187240107111600728002410160050800003024002012209122400102080000160000208000032000018000032000010
400024101195240041111600308000010160000800003024002712208822400102080000160000208000032000018000032000010
3164871048681937275429122650656485364122611800003024000812208872400102080000160000208000032000018000032000010
400024101132240041111600308000010160000800003024000812208612400102080000160000208000032000018000032000010
400024101145240041111600308000010160000800003024000812208482400102080000160000208000032000018000032000010
400024101158240041111600308000010160000800003024000812208452400102080000160000208000032000018000032000010
400024101150240041111600308000010160000800003024000812208512400102080000160000208000032000018000032000010
400024102551240050111600358000410160010800003024000812208682400102080000160000208000032000018000032000010
400024101139240041111600308000010160000800003024000812208672400102080000160000208000032000018000032000010