Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (single, H)

Test 1: uops

Code:

  ld2 { v0.h, v1.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005297033019120161002200410000300015284300001000200010004000110002000
63004293633005120041000200010000300015270300001000200010004000110002000
63004293743005120041000200010000300015270300001000200010004000110002000
63005293753006120041001200210000300015270300001000200010004000110002000
63004293553005120041000200010000300015270300001000200010004000110002000
63004293563005120041000200010000300015270300001000200010004000110002000
63004293563005120041000200010000300015270300001000200010004000110002000
63004293543005120041000200010000300015270300001000200010004000110002000
63004297113005120041000200010000300015274300001000200010004000110002000
63004293713005120041000200010000300015270300001000200010014004110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.h, v1.h }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120213801204010130018100013013030027100033208908120882830845297010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960288100155007540006100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120047801074010130006100003010330002100033208930120889030845647010830208100033000960216100035001540001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120167800304001130018100013004030027100033209086120941330846267001830028100033000960020100005000040001100002000040010
70024120042800144001130003100003001030000100003209187120946330847217001030020100003000060020100005000040001100002000040010
1025072333081048835607526372224364637526384100133210385120990030858567008830062100153004560020100005000040001100002000040010
70024120049800174001130006100003001030000100003208863120934330844187001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000100003208863120934330844187001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000100003209052120941330845937001030020100003000060020100005000040001100002000040010
70024120049800174001130006100003001030000100003209052120941330845937001030020100003000060108100155007540006100002000040010
70024120062800174001130006100003001030000100003209052120941330845937001030020100003000060020100005000040001100002000040010
70024120134800174001130006100003001030000100003209160120945330846977001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000100003208863120934330844187001030020100003000060020100005000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.h, v1.h }[1], [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70205120151801204010130018100013013030027100033208915120888630845487010830208100033000960216100035001540001100002000040100
70204120047801074010130006100003010330002100033208736120887730843947010830208100033000960216100035001540001100002000040100
70205120074801144010630007100013013330032100033208925120894730845697010830208100033000960216100035001540001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100035001540001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100035001540001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100035001540001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960288100155007540006100002000040100
70204120064801074010130006100003010330002100033208736120887730843947010830208100033000960216100035001540001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100035001540001100002000040100
70204120040801044010130003100003010330002100033208736120887730843947010830208100033000960216100035001540001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120157800304001130018100013004030027100033209690120969230851947001830028100033000960020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120049800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70025120080800274001630010100013004330032100003209160120945330846937001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70025120080800274001630010100013004330032100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2513

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205100450240220101160100800191001600358000530024002312207252401142008000516000920080005320020180000320000100
400204100104240140101160035800041001600108000530024003412207722401142008000516000920280090320350280000320000100
400204100103240138101160034800031001600098000530024002312207302401142008000516000920080005320018180000320000100
400204100103240138101160034800031001600098000530024007512209352401142008000516000920080089320348180000320000100
400204100103240138101160034800031001600098000530024002312207302401142008000516000920080005320018180000320000100
400205100149240207101160082800241001600508009030024243012266492403662008009016017620080005320018180000320000100
400204100103240138101160034800031001600098000530024004712208262401142008000516000920080086320342180000320000100
400204100103240138101160034800031001600098000530024002312207302401142008000516000920080005320018180000320000100
400204100103240138101160034800031001600098008830024248512268772403602008008816017220080025320100180000320000100
400204100103240138101160034800031001600098000530024002312207302401142008000516000920080005320018180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2632

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025102919240130111601008001910160035800003024000712208002400102080000160000208000032000018000032000010
400024101819240027111600168000010160000800263024008512210532400882080026160052208000032000018000032000010
400025101587240095111600598002510160052800003024002212207012400102080000160000208000032000018000032000010
400024101159240027111600168000010160000800263024060812229602400882080026160052208000032000018000032000010
400024101178240027111600168000010160000800003024000712206412400102080000160000208000032000018000032000010
400024101144240027111600168000010160000800003024000712206172400102080000160000208000032000018000032000010
400024101194240027111600168000010160000800003024000712206732400102080000160000208000032000018000032000010
400025101379240093111600588002410160050800003024000712206682400102080000160000208000032000018000032000010
400024101194240027111600168000010160000800003024000712206212400102080000160000208000032000018000032000010
400024101203240027111600168000010160000800003024001412206692400102080000160000208000032000018000032000010