Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (single, S)

Test 1: uops

Code:

  ld2 { v0.s, v1.s }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630053079130171201410022004100030001536230001000200010004000110002000
630042939130091200810002000100030001528430001000200010004000110002000
630042939630051200410002000100030001527030001000200010004000110002000
630042939530051200410002000100030001527030001000200010004000110002000
630042937830031200210002000100030001527030001000200010004000110002000
630042939130031200210002000100030001528430001000200010004000110002000
630042978930051200410002000100030021527630001000200010024004110002000
630042984430051200410002000100030001527030001000200010004000110002000
630042953030031200210002000100230061531930061002200410004000110002000
630042959530031200210002000100030001527230001000200010014004110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.s, v1.s }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70204120057801074010130006100003010330002100033208942120889630845747010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208741120881830843877010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70205120123801144010630007100013013330032100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100
70204120042801044010130003100003010330002100033208790120889730844447010830208100033000960216100035001540001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120211800304001130018100013004030027100003208961120932230844967001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70025120080800274001630010100013004330032100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060092100125006040006100002000040010
70024120047800174001130006100003001030000100033209042120945330845957001830028100033000960020100005000040001100002000040010
70024120049800174001130006100003001030000100003209052120941530845957001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010
70024120047800174001130006100003001030000100003208998120939330845437001030020100003000060020100005000040001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.s, v1.s }[1], [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70206120187801304010630022100023016030059100033208908120882830845297010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70204120049801074010130006100003010330002100033208979120896730846197010830208100033000960216100035001540001100002000040100
70358121180802594019030023100463023630064100373210360120928730859097032230314100393011560216100035001540001100002000040100
70205120131801204010630013100013013330032100033208930120888830845647010830208100033000960216100035001540001100002000040100
70204120047801074010130006100003010330002100033208952120895830845957010830208100033000960216100035001540001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100035001540001100002000040100
70205120124801174010630010100013013330032100033209006120898030846477010830208100033000960216100035001540001100002000040100
70204120047801074010130006100003010330002100033208925120894730845697010830208100033000960216100035001540001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
70025120156800304001130018100013004030027100033210814121010330862927001830028100033000960020100005000040001100002000040010
70024120042800144001130003100003001030000100003208863120934330844207001030020100003000060020100005000040001100002000040010
70024120040800144001130003100003001030000100003208809120932330843687001030020100003000060036100035001540001100002000040010
70024120042800144001130003100003001330002100003208880120929230844237001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000100003208863120934330844187001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000100003208863120934330844187001030020100003000060020100005000040001100002000040010
70024120042800144001130003100003001030000100003208863120934330844187001030020100003000060036100035001540001100002000040010
70024120040800144001130003100003001330002100033208826120937230843947001830028100033000960036100035001540001100002000040010
70024120040800144001130003100003001330002100153211043121021530865207009030065100153004460036100035001540001100002000040010
70024120040800144001130003100003001330002100003208809120932330843687001030020100003000060020100005000040001100002000040010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2512

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205100521240220101160100800191001600358000530024001512207812401142008000516000920080005320018180000320000100
400204100103240130101160025800041001600108000530024002312205782401142008000516000920080005320018180000320000100
400204100097240128101160024800031001600098000530024002312205782401142008000516000920080027320104180000320000100
400204100097240128101160024800031001600098000530024002312205782401142008000516000920080005320018180000320000100
400204100097240128101160024800031001600098002630024008612208842401762008002616005020080005320018180000320000100
400204100097240128101160024800031001600098000530024003512206182401142008000516000920080005320018180000320000100
400204100097240128101160024800031001600098000530024004212206422401142008000516000920080005320018180000320000100
400204100097240128101160024800031001600098000530024002312205782401142008000516000920080005320018180000320000100
400204100097240128101160024800031001600098000530024002312205782401142008000516000920080005320018180000320000100
400204100097240128101160024800031001600098000530024002312205782401142008000516000920080005320018180000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2624

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025103075240132111601018002010160036800053024003612212232400242080005160009208000032000018000032000010
400024102098240041111600308000010160000800003024003912207442400102080000160000208000032000018000032000010
400024100985240031111600208000010160000800003024000812206272400102080000160000208000032000018000032000010
400024100952240031111600208000010160000800003024002112209682400102080000160000208000032000018000032000010
400024100979240031111600208000010160000800003024000812206482400102080000160000208000032000018000032000010
400024100979240031111600208000010160000800003024102412247562400102080000160000208000032000018000032000010
400024100993240031111600208000010160000800003024000812206632400102080000160000208000032000018000032000010
400024100978240031111600208000010160000800003024000812206202400102080000160000208000032000018000032000010
400024101150240031111600208000010160000800003024001512206572400102080000160000208002532009818000032000010
400024101030240031111600208000010160000800003024002112206242400102080000160000208000032000018000032000010