Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (single, post-index, B)

Test 1: uops

Code:

  ld2 { v0.b, v1.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005296584019100320141002100220041000300030001528440001000200020004000100110002000
63004294094005100120041000100020001000300030001528440001000200020004000100110002000
63004294684005100120041000100020001000300030001528440001000200020004000100110002000
63004293754005100120041000100020001000300030001528440001000200020004000100110002000
63004294204005100120041000100020001000300030001528440001000200020004000100110002000
63004294164005100120041000100020001000300030001528440001000200020004000100110002000
63004293564005100120041000100020001000300030001528440001000200020004000100110002000
63004293904005100120041000100020001000300030001528440001000200020004000100110002000
63004293954005100120041000100020001000300030001528440001000200020004000100110002000
63004294224005100120041000100020001000300030001528440001000200020004000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.b, v1.b }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015090121501023001810001401323003210012319961894941229067128018130238100133003760216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710012320066994987329077708018230239100123003760216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020512007590115501073000710001401353003510003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710012319953694949629068408018230239100123003760216200065001550001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015590031500123001810001400423003110003319937694970429094048002430028100033000960020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002512008090028500173001010001400453003410000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060096200265006150007100002000040010
7002412007590020500113000910000400143000610012320160595036729113488009130058100123003760020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.b, v1.b }[1], [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2442

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512255490121501023001810001401323003210003326398696849129584508011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412251490107501013000610000401043000710003326436696873029590378011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710012326395696857829583848018230239100123003760216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2915

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512312290031500123001810001400423003110000327788197296029718598001030020100003000060020200005000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200005000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200005000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200005000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200005000050001100002000040010
7002512307590028500173001010001400453003510000327677497259129707998001030020100003000060020200005000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200005000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200005000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060020200005000050001100002000040010
7002412291590017500113000610000400103000010000327677497259129707998001030020100003000060096200265006150006100002000040010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205120272320243801211601028002080120160034800042403122400201239974320116200800041600082001600083200168000480000320000100
400205120142320199801201600608001980120160038800042403122400191240355320116200800041600082001600083200168000380000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400204120096320127801041600208000380104160008800042403122400191239889320116200800041600082001600403200768002180000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025120799320153800311601028002080031160034800042400422400201237056320026208000416000820160000320000800018000032000010
400024120043320031800111600208000080010160000800002400302400081240127320010208000016000020160040320076800208000032000010
400024120049320031800111600208000080010160000800002400302400081240146320010208000016000020160000320000800018000032000010
400024120043320031800111600208000080010160000800002400302400081240136320010208000016000020160000320000800018000032000010
400024120044320031800111600208000080010160000800002400302400081240157320010208000016000020160000320000800018000032000010
400024120043320031800111600208000080010160000800002400302400081240123320010208000016000020160000320000800018000032000010
400024120043320031800111600208000080010160000800002400302400081240145320010208000016000020160040320076800208000032000010
400024120043320031800111600208000080010160000800002400302400081240134320010208000016000020160000320000800018000032000010
400024120043320031800111600208000080010160000800002400302400081240147320010208000016000020160000320000800018000032000010
400024120143320031800111600208000080010160000800002400302400711240283320010208000016000020160000320000800018000032000010