Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (single, post-index, D)

Test 1: uops

Code:

  ld2 { v0.d, v1.d }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005305304029100720161006100620121000300030001528440001000200020004000100110002000
63004297134005100120041000100020001000300030001528440001000200020004000100110002000
63004296954005100120041000100020001000300030001528440001000200020004000100110002000
63004296904005100120041000100020001000300030001528440001000200020004000100110002000
63004297154005100120041000100020001000300030001528440001000200020004000100110002000
63004297214005100120041000100020001000300030001528440001000200020004000100110002000
63004297594005100120041000100020001000300030001528440001000200020004000100110002000
63004297224005100120041000100020001000300030001528440001000200020004000100110002000
63004298034005100120041000100020001000300030001528440001000200020004000100110002000
63004297284005100120041000100020001000300030001528440001000200020004000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.d, v1.d }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015490121501023001810001401323003310003319923094930729064288011430208100033000960216200065001550001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200065001550001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200065001550001100002000040100
7020412004990107501013000610000401043000710003320206795035929093408011430208100033000960216200065001550001100002000040100
7020412004990107501013000610000401043000710012319974794955729068738018230239100123003760216200065001550001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200065001550001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200065001550001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200065001550001100002000040100
7020412004990107501013000610000401043000710003319934094945029067428011430208100033000960216200065001550001100002000040100
7020412004990107501013000610000401043000710003320131195010729086248011430208100033000960216200065001550001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015290031500123001810001400423003210012319977094975629097158009130058100133003760036200065001550001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.d, v1.d }[1], [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2437

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512254790118501023001510001401323003210012326580096905229600408018430240100133003760218200085001550001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200065001550001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200065001550001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200065001550001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200065001550001100002000040100
7020512247290114501063000710001401353003310003326377296853729584788011430208100033000960216200065001550001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200065001550001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200065001550001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960216200065001550001100002000040100
7020412243790104501013000310000401043000710003326377296853729584788011430208100033000960276200265006150007100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2910

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002612311290041500173002210002400733005910003327933197333629731438002330028100033000960020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060096200265006150007100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010012328116997403029750288009130058100133003760260200745018450041100002000040010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5016

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205120261320237801191601008001880120160034800042403122400121240460320116200800041600082001600083200168000480000320000100
400204120126320161801041600548000380104160008800042403122400121240902320116200800041600082001600083200168000480000320000100
400204120126320161801041600548000380104160008800042403122400121240902320116200800041600082001600383200768001980000320000100
400204120126320161801041600548000380104160008800042403122400121240980320116200800041600082001600083200168000480000320000100
400204120126320161801041600548000380104160008800042403122400121240902320116200800041600082001600083200168000480000320000100
400204120126320161801041600548000380104160008800042403122400121240902320116200800041600082001600083200168000480000320000100
400204120114320152801041600458000380104160008800042403122400121240902320116200800041600082001600083200168000480000320000100
400204120126320161801041600548000380104160008800042403122400121240902320116200800041600082001600083200168000480000320000100
400204120126320161801041600548000380104160008800042403122400121240902320116200800041600082001600083200168000480000320000100
400204120126320161801041600548000380104160008800042403122400121240902320116200800041600082001600083200168000480000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025120883320149800301601008001980030160034800042400422400201241027320026208000416000820160034320068800188000032000010
400024120088320031800111600208000080010160000800002400302400081238507320010208000016000020160000320000800018000032000010
400024120054320031800111600208000080010160000800002400302400081238475320010208000016000020160000320000800018000032000010
400024120057320031800111600208000080010160000800002400302400081238488320010208000016000020160000320000800018000032000010
400024120057320031800111600208000080010160000800002400302400081238471320010208000016000020160000320000800018000032000010
400024120051320031800111600208000080010160000800002400302400081238463320010208000016000020160040320076800198000032000010
400024120055320031800111600208000080010160000800002400302400081238477320010208000016000020160000320000800018000032000010
400024120050320031800111600208000080010160000800002400302400081238542320010208000016000020160000320000800018000032000010
400024120051320031800111600208000080010160000800002400302400081240230320010208000016000020160000320000800018000032000010
400024120051320031800111600208000080010160000800002400302400081238467320010208000016000020160000320000800018000032000010