Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (single, post-index, H)

Test 1: uops

Code:

  ld2 { v0.h, v1.h }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005297854019100320141002100220041000300030001529040001000200020004000100110002000
63004296664003100120021000100020001000300030001527440001000200020004000100110002000
63004297834003100120021000100020001000300030001527440001000200020004000100110002000
63004300694003100120021000100020001000300030001527440001000200020004000100110002000
63004296784003100120021000100020001000300030001527440001000200020004000100110002000
63004296844003100120021000100020001000300030001527440001000200020004000100110002000
63004296574003100120021000100020001000300030001527440001000200020004000100110002000
63004296584003100120021000100020001000300030001527440001000200020004000100110002000
63004296574003100120021000100020001000300030001527340001000200020004000100110002000
63004296534003100120021000100020001000300030001527440001000200020004000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.h, v1.h }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015690121501023001810001401323003210003319919794924829062978011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710012319985694958929071608018230238100133003760216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710012319955894950129067298018230239100123003760216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015290031500123001810001400423003110003319931594963029093418002330028100033000960036200065001550001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010009319973594975529097138007630049100093002860020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002412004790017500113000610000400103000010000319935094965329092828001030020100003000060020200005000050001100002000040010
7002512008190029500183001010001400453003510000319935094965329092828001030020100003000060020200005000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.h, v1.h }[1], [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2442

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512268790121501023001810001401323003210003326407696851929584958011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326406796857029586358011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960278200285006550007100002000040100
7020412244490107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412252290107501013000610000401043000710003326393496858629586298011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2908

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512312190031500123001810001400423003110003327661197258729707508002430028100033000960020200005000050001100002000040010
7002412291690014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002512296890024500163000710001400453003310000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002512309590024500163000710001400453003410000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205120253320243801211601028002080120160034800042403122400121239798320116200800041600082001600083200168000480000320000100
400204120111320141801041600348000380104160008800042403122400121240330320116200800041600082001600083200168000480000320000100
400204120104320141801041600348000380104160008800192403572400571240538320176200800191600382001600083200168000480000320000100
400204120104320141801041600348000380104160008800042403122400121240330320116200800041600082001600083200168000480000320000100
400204120104320141801041600348000380104160008800042403122400121240580320116200800041600082001600083200168000480000320000100
400204120104320141801041600348000380104160008800042403122400121240330320116200800041600082001600083200168000480000320000100
400204120104320141801041600348000380104160008800042403122400121240330320116200800041600082001600083200168000480000320000100
400204120104320141801041600348000380104160008800212403632405431241316320180200800211600382001600083200168000480000320000100
400204120096320131801041600248000380104160008800042403122400201240126320116200800041600082001600083200168000480000320000100
400204120096320131801041600248000380104160008800042403122400201240126320116200800041600082001600083200168000480000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025120839320151800301601028001980031160034800042400422400201241140320026208000416000820160000320000800018000032000010
400024120051320041800151600228000480014160008800002400302400071239219320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071243192320010208000016000020160000320000800018000032000010
400024120051320037800141600208000380014160008800202400902400681236837320088208002016003820160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239093320010208000016000020160000320000800018000032000010
400024120051320037800141600208000380014160008800002400302400071243170320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239254320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400081236363320010208000016000020160000320000800018000032000010
400025120084320099800291600528001880030160038800002400302401331239247320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239041320010208000016000020160000320000800018000032000010