Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (single, post-index, S)

Test 1: uops

Code:

  ld2 { v0.s, v1.s }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63005297184021100320161002100220041000300030001528440001000200020004000100110002000
63004293514005100120041000100020001000300030001528440001000200020004000100110002000
63004293504005100120041000100020001000300030001528440001000200020004000100110002000
63004293864005100120041000100020001000300030001528440001000200020004000100110002000
63004293914005100120041000100020001000300030001528440001000200020004000100110002000
63004293504005100120041000100020001000300030001528440001000200020004000100110002000
63004293514005100120041000100020001000300030001528440001000200020004000100110002000
63004295784003100120021000100020001000300030001528640001000200020004000100110002000
63004298754005100120041000100020001000300030001528440001000200020004000100110002000
63004293874005100120041000100020001000300030001528440001000200020004000100110002000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.s, v1.s }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512015690121501023001810001401323003210003319928294937729065908011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020512007590115501073000710001401353003510003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020412004290104501013000310000401043000710003319915194939429065678011430208100033000960216200065001550001100002000040100
7020512013590121501103001010001401373003610003319931394944829067168011430208100033000960216200065001550001100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512015790031500123001810001400423003210003319936994964629093498002430028100033000960020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060096200265006150007100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010
7002412004990017500113000610000400103000010000319940494966929093328001030020100003000060020200005000050001100002000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.s, v1.s }[1], [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2442

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7020512254790121501023001810001401323003210012326429696862229587848018230240100133003760218200085001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020512246790118501073001010001401353003510003326431296871329589908011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960216200065001550001100002000040100
7020412244290107501013000610000401043000710003326390796857729586038011430208100033000960334200445010950012100002000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.2908

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
7002512302290031500123001810001400423003210003327653497250929705668002430028100033000960036200065001550001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010009327980597352829736178007830050100103002860020200005000050001100002000040010
7002412290890014500113000310000400103000010000327861097320429725488001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002412290890014500113000310000400103000010000327658597253529706248001030020100003000060020200005000050001100002000040010
7002512290190025500173000710001400453003510000327658597253529706248001030020100003000060020200005000050001100002000040010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.s, v1.s }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400205120291320237801191601008001880120160034800042403122400201240068320116200800041600082001600103200168000580000320000100
400205120129320193801211600528002080120160038800042403122401591240166320116200800041600082001600103200168000480000320000100
400204120096320127801041600208000380104160008800042403122400191239889320116200800041600082001600083200168000480000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000480000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400205120129320189801201600508001980120160038800052403152400221239597320118200800051600082001600083200168000480000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000480000320000100
400204120095320125801031600208000280104160008800042403122400191239889320116200800041600082001600083200168000380000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
400025120888320153800311601028002080030160034800002400302400081241877320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239248320010208000016000020160038320076800198000032000010
400024120042320027800111600168000080010160000800002400302400071239079320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239242320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239260320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239075320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239051320010208000016000020160032320060800178000032000010
400024120042320027800111600168000080010160000800002400302400071239076320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239045320010208000016000020160000320000800018000032000010
400024120042320027800111600168000080010160000800002400302400071239053320010208000016000020160000320000800018000032000010