Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (16B)

Test 1: uops

Code:

  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.006

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
640053107340441304110023006100030002305440001000300010003000110003000
640042949740071300610003000100030002305140001000300010003000110003000
640042947140071300610003000100030002305140001000300010003000110003000
640042949140071300610003000100030002305140001000300010003000110003000
640042946740071300610003000100030002305140001000300010003000110003000
640042946840071300610003000100030002305140001000300010003000110003000
640042947240071300610003000100030002305140001000300010003000110003000
640042949040071300610003000100030002305140001000300010003000110003000
640042946840071300610003000100030002305140001000300010003000110003000
640042946740071300610003000100030002305140001000300010003000110003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320206120212320234101240105800281002400838000430024001518529423201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120074320126101240022800031002400118000430024011724004523201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108002430024025720511853201902008002524007520080005240015180000240000100
320204120055320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000530024041724005743201162008000524001520080005240015180000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025120185320094112400708001310240037800043024004324002443200242080005240015208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024002724001923200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208002524007518000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010