Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (1D)

Test 1: uops

Code:

  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.003

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
65005302605045130402004300620006000230605000200030000200060001200030000
65004299265004130032000300020006000230345000200030000200060001200030000
65004298175004130032000300020006000230305000200030000200060001200030000
65004297635004130032000300020006000230315000200030000200060001200030000
65004296685004130032000300020006000230315000200030000200060001200030000
65004296445004130032000300020006000230315000200030000200060001200030000
65004296515004130032000300020006000230315000200030000200060001200030000
65004296465004130032000300020006000230315000200030000200060001200030000
65004296935004130032000300020006000230315000200030000200060001200030000
65004296815004130032000300020006000230315000200030000200060001200030000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40020516017040022610124009716002810024003716000830048004619199714001192001600082400112001600084800221160000240000100
40020416003840013110124002416000610024001116000830048004619199674001192001600082400112001600084800221160000240000100
40020416003840013110124002416000610024001116000830048004619199674001192001600082400112001600084800221160000240000100
40020416003840013110124002416000610024001116003230048171619230774001782001600322400462001600084800221160000240000100
40020416003840013110124002416000610024001116000830048053019208284001192001600082400112001600084800221160000240000100
40020416004940012810124002116000610024001116000830048004019198974001192001600082400112001600084800221160000240000100
40020516007440016910124004416002410024004616000830048009019200494001192001600082400112001600084800221160000240000100
40020416003740012810124002116000610024001116000830048006019199314001192001600082400112001600564801621160000240000100
40020416006140012810124002116000610024001116000830048004019199014001192001600082400112001600084800221160000240000100
40020416003740012810124002116000610024001116000830048004019199014001192001600082400112001600084800221160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40002516016640013611240097160028102400371600323048010419207784000882016003224004620160008480022116000024000010
40002416004340003811240027160000102400001600003048002219202564000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048006419203324000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048002219202564000102016000024000020160000480000116000024000010
40002516007440008711240050160026102400461600003048002219202564000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048002219202564000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048002219202564000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048002219202564000102016000024000020160000480000116000024000010
40002516007440008711240050160026102400461600003048002219202564000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048002219202564000102016000024000020160000480000116000024000010