Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (2D)

Test 1: uops

Code:

  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.003

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
650052999550461304120043006200060002303650002000300020006000120003000
650042961450071300620003000200060002305750002000300020006000120003000
650042961350041300320003000200060002303650002000300020006000120003000
650042959550041300320003000200060002303650002000300020006000120003000
650042958950041300320003000200060002303650002000300020006000120003000
650042959650041300320003000200060002303650002000300020006000120003000
650042958050041300320003000200060002303650002000300020006000120003000
650042959950041300320003000200060002303650002000300020006000120003000
650042958850041300320003000200060002303650002000300020006000120003000
650042960950041300320003000200060002303650002000300020006000120003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40020516015440022610124009716002810024003716000830048006019201034001192001600082400112001600084800221160000240000100
40020416004240013810124003116000610024001116000830048005819200934001192001600082400112001600084800221160000240000100
40020416004240013810124003116000610024001116000830048004619200694001192001600082400112001600084800221160000240000100
40020516007840018410124005716002610024004616010430048340219256774003552001601042401512001600084800221160000240000100
40020516007940020110124007416002610024004616000830048017419203034001192001600082400112001600084800221160000240000100
40020416004240013810124003116000610024001116000830048009619201574001192001600082400112001600084800221160000240000100
40020416004240013810124003116000610024001116000830048004619200694001192001600082400112001600084800221160000240000100
40020416004240013810124003116000610024001116000830048004619200694001192001600082400112001600084800221160000240000100
40020416004240013810124003116000610024001110001048002348403117913125039454901002091464072001600084800221160000240000100
40020416037140037410124017116010210024015116010430048392819266014003552001601042401512001601044803021160000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40002516017040013611240097160028102400371600083048005819203494000292016000824001120160000480000116000024000010
40002516007440008711240050160026102400461600003048002219202564000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048004219202944000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048005419203124000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048005219203104000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048004019202904000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600083048012419206804000292016000824001120160032480092116000024000010
40002416003640002611240015160000102400001600003048062019249394000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048004619203004000102016000024000020160000480000116000024000010
40002416003740002911240018160000102400001600003048004819203024000102016000024000020160000480000116000024000010