Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (2S)

Test 1: uops

Code:

  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.006

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6400529811404413041100203006100030002305140001000300010003000110003000
6400429832400713006100003000100030022305740001000300010003000110003000
6400429538400713006100003000100030002305140001000300010003000110003000
6400429707400713006100003000100030002305140001000300010003000110003000
6400429775400713006100003000100030002305140001000300010003000110003000
6400429508400713006100003000100030002305140001000300010003000110003000
6400429486400713006100003000100030002305140001000300010003000110003000
6400429494400713006100003000100030002305140001000300010003000110003000
6400429496400713006100003000100030002305140001000300010003000110003000
6400429529400713006100003000100030002305140001000300010003000110003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320205120164320188101240074800131002400368000430024001516945163201142008000524001520080022240066180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120062320130101240026800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024002524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024002124004923201142008000524001520080005240015180000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025120153320094112400708001310240036800003024000318243563200102080000240000208000024000018000024000010
320025120083320085112400548002010240066800003024051924006513200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024001224001803200102080000240000208004024012018000024000010
320024120421320309132402178007912240237800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208002424007218000024000010
320025120098320087112400568002010240064800003024003924001803200102080000240000208000524001518000024000010
320024120048320026112400158000010240000800003024000324002223200102080000240000208000024000018000024000010
320024120048320026112400158000010240000800003024000324002223200102080000240000208000024000018000024000010
320024120048320026112400158000010240000800003024000324002223200102080000240000208000024000018000024000010