Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (4H)

Test 1: uops

Code:

  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.006

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
64005303264081130741006301810000300023051400001000300010003000110003000
64004296264007130061000300010000300023051400001000300010003000110003000
64004294794007130061000300010000300023051400001000300010003000110003000
64004294734007130061000300010000300023051400001000300010003000110003000
64004295034007130061000300010000300023051400001000300010003000110003000
64004295134007130061000300010000300023051400001000300010003000110003000
64004294764007130061000300010000300023051400001000300010003000110003000
64004295184007130061000300010000300023051400001000300010003000110003000
64004295364007130061000300010000300023051400001000300010003000110003000
64004295074007130061000300010000300023051400001000300010003000110003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320205120159320184101240070800131002400368000430024001516944643201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001924004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024002524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120070320126101240022800031002400118002430024021521875403201902008002524007520080005240015180000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025120168320098112400748001310240036800003024002224003843200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000324003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000324003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000324003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000324003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000324003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000324003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000924003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000324003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000324003783200102080000240000208000024000018000024000010