Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (4S)

Test 1: uops

Code:

  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.003

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
640052975840461304310023006100030002305140001000300010003000110003000
640042949940041300310003000100030002303040001000300010003000110003000
640042950540041300310003000100030002303040001000300010003000110003000
640042948440041300310003000100030002303040001000300010003000110003000
640042948040041300310003000100030002303040001000300010003000110003000
640042947240071300610003000100030012303340001000300010003000110003000
640042988940041300310003000100030002303040001000300010003000110003000
640042962040041300310003000100030002303040001000300010003000110003000
640042946840041300310003000100030002303040001000300010003000110003000
640042948040041300310003000100030002303040001000300010003000110003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320205120322320184101240070800131002400378000430024002617651483201142008000524001520080005240015180000240000100
320205120091320179101240058800201002400648000430024002318529423201142008000524001520080005240015180000240000100
3648892241693621852802224014494019271812401598000430024002519006063201142008000524001520080005240015180000240000100
320204120046320118101240014800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120046320118101240014800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120046320118101240014800031002400108002330024007424010703201872008002424007220080005240015180000240000100
320204120046320118101240014800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120046320118101240014800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120055320126101240022800031002400108000430024004324004403201142008000524001520080005240015180000240000100
320205120091320182101240061800201002400668000430024002524004403201142008000524001520080005240015180000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025120158320094112400708001310240036800003024000324003783200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800233024007122864803200972080024240072208000024000018000024000010
320024120054320033112400228000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024002524001803200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800243024007519734213201002080025240075208000024000018000024000010
320024120054320033112400228000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120054320033112400228000010240000800003024000424001803200102080000240000208000024000018000024000010