Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (8B)

Test 1: uops

Code:

  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.003

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
640052976040441304110023006100030002306040001000300010003000110003000
640042950640071300610003000100030002303640001000300010003000110003000
640042948340041300310003000100030002303640001000300010003000110003000
640042949140041300310003000100030002303640001000300010003000110003000
640042948740041300310003000100030002303640001000300010003000110003000
640042947140041300310003000100030002303640001000300010003000110003000
640042948740041300310003000100030002303640001000300010003000110003000
640043008140071300610003000100030002303040001000300010003000110003000
640042958140041300310003000100030002303040001000300010003000110003000
640042968940041300310003000100030002303040001000300010003000110003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320205120154320184101240070800131002400378000430024001518529423201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108002330024007023242443201872008002424007220080005240015180000240000100
320204120065320127101240023800031002400108000430024002321123383201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024002524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320205120093320183101240062800201002400668000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100
320204120056320126101240022800031002400108000430024001524004923201142008000524001520080005240015180000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025120156320094112400708001310240037800043024001524004923200242080005240015208000524001518000024000010
320024120056320033112400228000010240000800003024000324004303200102080000240000208000024000018000024000010
3200241200563200331124002280000102400005910559617820715258032363839959105177243208000024000018000024000010
320024120056320033112400228000010240000800003024001824004303200102080000240000208000024000018000024000010
320024120056320033112400228000010240000800003024000324005083200102080000240000208000024000018000024000010
320024120056320033112400228000010240000800003024000324004303200102080000240000208000024000018000024000010
320024120068320033112400228000010240000800003024010624004363200102080000240000208000024000018000024000010
320024120056320033112400228000010240000800003024006323518523200102080000240000208000024000018000024000010
320024120056320033112400228000010240000800003024002624004363200102080000240000208000024000018000024000010
320024120056320033112400228000010240000800003024000324004303200102080000240000208000024000018000024000010