Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (8H)

Test 1: uops

Code:

  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.003

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
64005299844044130411002300610000300023060400001000300010003000110003000
64004295014007130061000300010000300023036400001000300010003000110003000
64004294964004130031000300010000300023036400001000300010003000110003000
64004294994004130031000300010000300023036400001000300010003000110003000
64004294924004130031000300010000300023036400001000300010003000110003000
64004294944004130031000300010000300023036400001000300010003000110003000
64004296354004130031000300010000300023036400001000300010003000110003000
64004303234004130031000300010010301123084400401001300310003000110003000
6400429918400413003100030002633266016527455326651700435444431282321910003000110003000
64004295824004130031000300010000300023036400001000300010003000110003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320205120182320184101240070800131002400368000430024013619232163201142008000524001520080005240015180000240000100
320205120090320181101240060800201002400648000430024001616942563201142008000524001520080005240015180000240000100
320204120046320118101240014800031002400108000430024001624002423201142008000524001520080005240015180000240000100
320204120046320118101240014800031002400108000430024001624002423201142008000524001520080005240015180000240000100
320204120046320118101240014800031002400108000430024001624002423201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001624002423201142008000524001520080005240015180000240000100
320205120091320183101240062800201002400668000430024013824004523201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001524004403201142008000524001520080005240015180000240000100
320204120054320126101240022800031002400108000430024001624002423201142008000524001520080005240015180000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025120165320098112400748001310240036800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208002524007518000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208000024000018000024000010
320024120046320025112400148000010240000800003024000424001803200102080000240000208002524007518000024000010
320025120094320079112400488002010240064800003024000624001803200102080000240000208000024000018000024000010