Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3R (post-index, 16B)

Test 1: uops

Code:

  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.006

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
64005296175046100330411002100230061000300030002306050001000300020003000100110003000
64004294285007100130061000100030001000300030002306050001000300020003000100110003000
64004294295007100130061000100030001000300030002306050001000300020003000100110003000
64004294295007100130061000100030001000300030002306050001000300020003000100110003000
64004294525007100130061000100030001000300030002306050001000300020003000100110003000
64004294275007100130061000100030001000300030002306050001000300020003000100110003000
64004294515007100130061000100030001000300030002306050001000300020003000100110003000
64004294295007100130061000100030001000300030002306050001000300020003000100110003000
64004296475007100130061000100030001000300030012306350001000300020003000100110003000
64004295515007100130061000100030001000300030002306950001000300020003000100110003000

Test 2: throughput

Count: 8

Code:

  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320205120157400197801142400708001380114240036800042403122400151701710400118200800052400152001600102400158000480000240000100
320204120477400543801902402668008780190240262800042403122400822119360400118200800052400152001600102400158000480000240000100
320204120048400122801042400158000380104240010800042403122400152400284400118200800052400152001600102400158000480000240000100
320204120048400122801042400158000380104240010800042403122400152400284400118200800052400152001602622403938013080000240000100
320204121283401169803142406428021380315240641802152409452463371756336401171200802152406452001600102400158000480000240000100
320204120048400122801042400158000380104240010800262403782400811974011400226200800262400782001600102400158000480000240000100
320204120048400122801042400158000380104240010800042403122400152400284400118200800052400152001600102400158000480000240000100
320204120048400122801042400158000380104240010800042403122400152400284400118200800052400152001600102400158000480000240000100
320204120048400122801042400158000380104240010800042403122400152400284400118200800052400152001600102400158000480000240000100
320204120048400122801042400158000380104240010800042403122400152400284400118200800052400152001600102400158000480000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
320025120151400107800242400708001380024240036800002400302400041896162400010208000024000020160000240000800018000024000010
320024120046400025800112400148000080010240000800002400302400042400180400010208000024000020160000240000800018000024000010
320024120046400025800112400148000080010240000800002400302400042400180400010208000024000020160000240000800018000024000010
320024120046400025800112400148000080010240000800002400302400042400180400010208000024000020160052240078800258000024000010
320024120046400025800112400148000080010240000800002400302400042400180400010208000024000020160000240000800018000024000010
320024120046400025800112400148000080010240000800002400302400042400180400010208000024000020160000240000800018000024000010
320024120046400025800112400148000080010240000800002400302400042400180400010208000024000020160000240000800018000024000010
320024120046400025800112400148000080010240000800002400302400042400180400010208000024000020160000240000800018000024000010
320024120046400025800112400148000080010240000800262401082400822339549400136208002624007820160000240000800018000024000010
320024120046400025800112400148000080010240000800002400302400042400180400010208000024000020160000240000800018000024000010